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VME64x core
Commit 781e4153 authored by Tom Levens's avatar Tom Levens
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Remove VME_Init component 

The VME_Init component was not needed as all of the CR data comes from
generics. Therefore it has been removed to help reduce the footprint of
the core (Feature #768).
Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent 8f0ec377
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Showing with 148 additions and 460 deletions
hdl/vme64x-core/rtl/Manifest.py
View file @ 781e4153
...@@ -8,7 +8,6 @@ files = [ "xvme64x_core.vhd", ...@@ -8,7 +8,6 @@ files = [ "xvme64x_core.vhd",
"VME_CR_CSR_Space.vhd", "VME_CR_CSR_Space.vhd",
"VME_CRAM.vhd", "VME_CRAM.vhd",
"VME_Funct_Match.vhd", "VME_Funct_Match.vhd",
"VME_Init.vhd",
"VME_IRQ_Controller.vhd", "VME_IRQ_Controller.vhd",
"VME_swapper.vhd", "VME_swapper.vhd",
"VME_Wb_master.vhd"] "VME_Wb_master.vhd"]
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 781e4153
...@@ -345,7 +345,36 @@ begin ...@@ -345,7 +345,36 @@ begin
g_clock => g_clock, g_clock => g_clock,
g_wb_data_width => g_wb_data_width, g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width, g_wb_addr_width => g_wb_addr_width,
g_cram_size => f_size(g_beg_cram, g_end_cram) g_beg_user_cr => g_beg_user_cr,
g_end_user_cr => g_end_user_cr,
g_beg_cram => g_beg_cram,
g_end_cram => g_end_cram,
g_beg_user_csr => g_beg_user_csr,
g_end_user_csr => g_end_user_csr,
g_f0_adem => g_f0_adem,
g_f0_amcap => g_f0_amcap,
g_f0_xamcap => g_f0_xamcap,
g_f1_adem => g_f1_adem,
g_f1_amcap => g_f1_amcap,
g_f1_xamcap => g_f1_xamcap,
g_f2_adem => g_f2_adem,
g_f2_amcap => g_f2_amcap,
g_f2_xamcap => g_f2_xamcap,
g_f3_adem => g_f3_adem,
g_f3_amcap => g_f3_amcap,
g_f3_xamcap => g_f3_xamcap,
g_f4_adem => g_f4_adem,
g_f4_amcap => g_f4_amcap,
g_f4_xamcap => g_f4_xamcap,
g_f5_adem => g_f5_adem,
g_f5_amcap => g_f5_amcap,
g_f5_xamcap => g_f5_xamcap,
g_f6_adem => g_f6_adem,
g_f6_amcap => g_f6_amcap,
g_f6_xamcap => g_f6_xamcap,
g_f7_adem => g_f7_adem,
g_f7_amcap => g_f7_amcap,
g_f7_xamcap => g_f7_xamcap
) )
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
......
hdl/vme64x-core/rtl/VME_Access_Decode.vhd
View file @ 781e4153
...@@ -165,7 +165,6 @@ entity VME_Access_Decode is ...@@ -165,7 +165,6 @@ entity VME_Access_Decode is
mainFSMreset : in std_logic; mainFSMreset : in std_logic;
decode : in std_logic; decode : in std_logic;
ModuleEnable : in std_logic; ModuleEnable : in std_logic;
InitInProgress : in std_logic;
Addr : in std_logic_vector(63 downto 0); Addr : in std_logic_vector(63 downto 0);
Ader0 : in std_logic_vector(31 downto 0); Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0); Ader1 : in std_logic_vector(31 downto 0);
...@@ -293,7 +292,7 @@ begin ...@@ -293,7 +292,7 @@ begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
CardSel <= '0'; CardSel <= '0';
Base_Addr <= (others => '0'); Base_Addr <= (others => '0');
if ModuleEnable = '1' and InitInProgress = '0' then if ModuleEnable = '1' then
for I in 0 to 7 loop for I in 0 to 7 loop
if s_func_sel(i) = '1' then if s_func_sel(i) = '1' then
CardSel <= '1'; CardSel <= '1';
...@@ -308,7 +307,8 @@ begin ...@@ -308,7 +307,8 @@ begin
s_func_sel <= s_Func_Match and s_Am_Match; s_func_sel <= s_Func_Match and s_Am_Match;
-- Check if the CR/CSR space is addressed -- Check if the CR/CSR space is addressed
Confaccess <= '1' when unsigned(BAR_i) = unsigned(Addr(23 downto 19)) and Confaccess <= '1'
Am = c_CR_CSR and InitInProgress = '0' else '0'; when unsigned(BAR_i) = unsigned(Addr(23 downto 19)) and Am = c_CR_CSR
else '0';
end Behavioral; end Behavioral;
hdl/vme64x-core/rtl/VME_Init.vhd deleted 100644 → 0
View file @ 8f0ec377
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_Init (VME_Init.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description: Read important CR data (like FUNC_ADEMs etc.) and store it
-- locally. This important CR data will be used in the decoder.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
entity VME_Init is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
CRAddr_i : in std_logic_vector(18 downto 0);
CRdata_i : in std_logic_vector(7 downto 0);
InitReadCount_o : out std_logic_vector(8 downto 0);
InitInProgress_o : out std_logic;
BEG_USR_CR_o : out std_logic_vector(23 downto 0);
END_USR_CR_o : out std_logic_vector(23 downto 0);
BEG_USR_CSR_o : out std_logic_vector(23 downto 0);
END_USR_CSR_o : out std_logic_vector(23 downto 0);
BEG_CRAM_o : out std_logic_vector(23 downto 0);
END_CRAM_o : out std_logic_vector(23 downto 0);
FUNC0_ADEM_o : out std_logic_vector(31 downto 0);
FUNC1_ADEM_o : out std_logic_vector(31 downto 0);
FUNC2_ADEM_o : out std_logic_vector(31 downto 0);
FUNC3_ADEM_o : out std_logic_vector(31 downto 0);
FUNC4_ADEM_o : out std_logic_vector(31 downto 0);
FUNC5_ADEM_o : out std_logic_vector(31 downto 0);
FUNC6_ADEM_o : out std_logic_vector(31 downto 0);
FUNC7_ADEM_o : out std_logic_vector(31 downto 0);
FUNC0_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC1_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC2_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC3_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC4_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC5_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC6_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC7_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC0_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC1_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC2_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC3_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC4_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC5_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC6_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC7_XAMCAP_o : out std_logic_vector(255 downto 0)
);
end VME_Init;
architecture Behavioral of VME_Init is
signal s_initReadCounter : unsigned(8 downto 0) := to_unsigned(0, InitReadCount_o'length);
signal s_initState : t_initState;
signal s_latchCRdata : std_logic := '0'; -- Stores read CR data
signal s_initInProgress : std_logic;
signal s_CRadd_offset : unsigned(18 downto 0);
signal s_CRaddr_base : unsigned(18 downto 0);
signal s_CRaddr : unsigned(18 downto 0);
signal s_latchCRdataPos : std_logic_vector(BEG_USER_CR to FUNC_ADEM);
-- CR image registers
signal s_FUNC_ADEM : t_FUNC_32b_array;
signal s_FUNC_AMCAP : t_FUNC_64b_array;
signal s_FUNC_XAMCAP : t_FUNC_256b_array;
signal s_BEG_USER_CSR : unsigned(23 downto 0) := (others => '0');
signal s_END_USER_CSR : unsigned(23 downto 0) := (others => '0');
signal s_BEG_USER_CR : unsigned(23 downto 0) := (others => '0');
signal s_END_USER_CR : unsigned(23 downto 0) := (others => '0');
signal s_BEG_CRAM : unsigned(23 downto 0) := (others => '0');
signal s_END_CRAM : unsigned(23 downto 0) := (others => '0');
begin
InitReadCount_o <= std_logic_vector(s_initReadCounter);
s_CRaddr <= unsigned(CRAddr_i);
p_coreInit : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
s_initState <= IDLE;
s_initReadCounter <= to_unsigned(0, s_initReadCounter'length);
s_latchCRdata <= '0';
else
case s_initState is
when IDLE =>
s_initReadCounter <= to_unsigned(0, s_initReadCounter'length);
s_latchCRdata <= '0';
s_initState <= SET_ADDR;
when SET_ADDR =>
s_initReadCounter <= s_initReadCounter+1;
s_latchCRdata <= '0';
s_initState <= GET_DATA;
when GET_DATA =>
s_initReadCounter <= s_initReadCounter;
s_latchCRdata <= '1';
if s_initInProgress = '1' then
s_initState <= SET_ADDR;
else
s_initState <= END_INIT;
end if;
when END_INIT => -- will wait in this state until reset
s_initReadCounter <= s_initReadCounter;
s_latchCRdata <= '0';
s_initState <= END_INIT;
when others =>
s_initState <= IDLE;
s_initReadCounter <= to_unsigned(0, s_initReadCounter'length);
s_latchCRdata <= '0';
end case;
end if;
end if;
end process;
s_initInProgress <= '1' when (s_initReadCounter <= (424)) else '0';
InitInProgress_o <= s_initInProgress;
s_CRadd_offset <= s_CRaddr - s_CRaddr_base;
process (s_latchCRdata, s_initReadCounter)
begin
s_latchCRdataPos <= (others => '0');
s_CRaddr_base <= (others => '0');
for I in c_CRinitAddr'range loop
if (s_initReadCounter >= c_CRinitAddr(I).add) and
(s_initReadCounter <= (c_CRinitAddr(I).add + (c_CRinitAddr(I).len-1)))
then
s_CRaddr_base <= to_unsigned(c_CRinitAddr(I).add, s_CRaddr_base'length);
s_latchCRdataPos(I) <= s_latchCRdata;
exit;
end if;
end loop;
end process;
process (clk_i)
begin
if rising_edge(clk_i) then
for I in 0 to 2 loop
if (s_latchCRdataPos(BEG_USER_CR) = '1') and (unsigned(s_CRadd_offset) = I) then
s_BEG_USER_CR(((3-I)*8-1) downto (2-I)*8) <= unsigned(CRdata_i);
end if;
if s_latchCRdataPos(END_USER_CR) = '1' and (unsigned(s_CRadd_offset) = I) then
s_END_USER_CR(((3-I)*8-1) downto (2-I)*8) <= unsigned(CRdata_i);
end if;
if (s_latchCRdataPos(BEG_USER_CSR) = '1') and (unsigned(s_CRadd_offset) = I) then
s_BEG_USER_CSR(((3-I)*8-1) downto (2-I)*8) <= unsigned(CRdata_i);
end if;
if (s_latchCRdataPos(END_USER_CSR) = '1') and (unsigned(s_CRadd_offset) = I) then
s_END_USER_CSR(((3-I)*8-1) downto (2-I)*8) <= unsigned(CRdata_i);
end if;
if (s_latchCRdataPos(BEG_CRAM) = '1') and (unsigned(s_CRadd_offset) = I) then
s_BEG_CRAM(((3-I)*8-1) downto (2-I)*8) <= unsigned(CRdata_i);
end if;
if (s_latchCRdataPos(END_CRAM) = '1') and (unsigned(s_CRadd_offset) = I) then
s_END_CRAM(((3-I)*8-1) downto (2-I)*8) <= unsigned(CRdata_i);
end if;
end loop;
for I in 0 to 7 loop
if (s_latchCRdataPos(FUNC_AMCAP) = '1') and (unsigned(s_CRadd_offset(5 downto 3)) = I) then
for H in 0 to 7 loop
if (unsigned(s_CRadd_offset(2 downto 0)) = H) then
s_FUNC_AMCAP(I)(((8-h)*8-1) downto (7-h)*8) <= unsigned(CRdata_i);
end if;
end loop;
end if;
if (s_latchCRdataPos(FUNC_ADEM) = '1') and (unsigned(s_CRadd_offset(5 downto 2)) = I) then
for H in 0 to 3 loop
if (unsigned(s_CRadd_offset(1 downto 0)) = H) then
s_FUNC_ADEM(I)(((4-h)*8-1) downto (3-h)*8) <= unsigned(CRdata_i);
end if;
end loop;
end if;
if (s_latchCRdataPos(FUNC_XAMCAP) = '1') and (unsigned(s_CRadd_offset(7 downto 5)) = I) then
for H in 0 to 31 loop
if (unsigned(s_CRadd_offset(4 downto 0)) = H) then
s_FUNC_XAMCAP(I)(((32-h)*8-1) downto (31-h)*8) <= unsigned(CRdata_i);
end if;
end loop;
end if;
end loop;
end if;
end process;
BEG_USR_CR_o <= std_logic_vector(s_BEG_USER_CR);
END_USR_CR_o <= std_logic_vector(s_END_USER_CR);
BEG_USR_CSR_o <= std_logic_vector(s_BEG_USER_CSR);
END_USR_CSR_o <= std_logic_vector(s_END_USER_CSR);
BEG_CRAM_o <= std_logic_vector(s_BEG_CRAM);
END_CRAM_o <= std_logic_vector(s_END_CRAM);
FUNC0_ADEM_o <= std_logic_vector(s_FUNC_ADEM(0));
FUNC1_ADEM_o <= std_logic_vector(s_FUNC_ADEM(1));
FUNC2_ADEM_o <= std_logic_vector(s_FUNC_ADEM(2));
FUNC3_ADEM_o <= std_logic_vector(s_FUNC_ADEM(3));
FUNC4_ADEM_o <= std_logic_vector(s_FUNC_ADEM(4));
FUNC5_ADEM_o <= std_logic_vector(s_FUNC_ADEM(5));
FUNC6_ADEM_o <= std_logic_vector(s_FUNC_ADEM(6));
FUNC7_ADEM_o <= std_logic_vector(s_FUNC_ADEM(7));
FUNC0_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(0));
FUNC1_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(1));
FUNC2_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(2));
FUNC3_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(3));
FUNC4_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(4));
FUNC5_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(5));
FUNC6_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(6));
FUNC7_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(7));
FUNC0_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(0));
FUNC1_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(1));
FUNC2_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(2));
FUNC3_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(3));
FUNC4_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(4));
FUNC5_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(5));
FUNC6_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(6));
FUNC7_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(7));
end Behavioral;
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 781e4153
...@@ -15,25 +15,23 @@ ...@@ -15,25 +15,23 @@
-- WBbus. -- WBbus.
-- --
-- _____________VME_bus________________ -- _____________VME_bus________________
-- | _______ | -- | |
-- | ______ | M | | -- | ______ _______ |
-- | | A D | | A F | ____| -- | | A D | | | ____|
-- | | C E | | I S | | W | -- | | C E | | M F | | W |
-- | | C C | | N M | | B | -- | | C C | | A S | | B |
-- VME | | E O | | | | | -- VME | | E O | | I M | | |
-- BUS | | S D | |_______| | M | -- BUS | | S D | | N | | M |
-- | | S E | | A | -- | | S E | | | | A |
-- | |______| | S | -- | |______| |_______| | S |
-- | ______ ___________ | T | -- | __________________ | T |
-- | | I | | OTHER || E | -- | | | | E |
-- | | N | | DATA & || R | -- | | OTHER DATA & | | R |
-- | | I | | ADDR ||____| -- | | ADDR PROCESS | |____|
-- | | T | | PROCESS | | -- | | | |
-- | |______| |___________| | -- | |__________________| |
-- |____________________________________| -- |____________________________________|
-- --
-- The INIT component performs the initialization of the core after the
-- power-up or reset.
-- The Access decode component decodes the address to check if the board is -- The Access decode component decodes the address to check if the board is
-- the responding Slave. This component is of fundamental importance, indeed -- the responding Slave. This component is of fundamental importance, indeed
-- only one Slave can answer to the Master! -- only one Slave can answer to the Master!
...@@ -75,7 +73,36 @@ entity VME_bus is ...@@ -75,7 +73,36 @@ entity VME_bus is
g_clock : integer; g_clock : integer;
g_wb_data_width : integer; g_wb_data_width : integer;
g_wb_addr_width : integer; g_wb_addr_width : integer;
g_cram_size : integer g_beg_user_cr : std_logic_vector( 23 downto 0);
g_end_user_cr : std_logic_vector( 23 downto 0);
g_beg_cram : std_logic_vector( 23 downto 0);
g_end_cram : std_logic_vector( 23 downto 0);
g_beg_user_csr : std_logic_vector( 23 downto 0);
g_end_user_csr : std_logic_vector( 23 downto 0);
g_f0_adem : std_logic_vector( 31 downto 0);
g_f0_amcap : std_logic_vector( 63 downto 0);
g_f0_xamcap : std_logic_vector(255 downto 0);
g_f1_adem : std_logic_vector( 31 downto 0);
g_f1_amcap : std_logic_vector( 63 downto 0);
g_f1_xamcap : std_logic_vector(255 downto 0);
g_f2_adem : std_logic_vector( 31 downto 0);
g_f2_amcap : std_logic_vector( 63 downto 0);
g_f2_xamcap : std_logic_vector(255 downto 0);
g_f3_adem : std_logic_vector( 31 downto 0);
g_f3_amcap : std_logic_vector( 63 downto 0);
g_f3_xamcap : std_logic_vector(255 downto 0);
g_f4_adem : std_logic_vector( 31 downto 0);
g_f4_amcap : std_logic_vector( 63 downto 0);
g_f4_xamcap : std_logic_vector(255 downto 0);
g_f5_adem : std_logic_vector( 31 downto 0);
g_f5_amcap : std_logic_vector( 63 downto 0);
g_f5_xamcap : std_logic_vector(255 downto 0);
g_f6_adem : std_logic_vector( 31 downto 0);
g_f6_amcap : std_logic_vector( 63 downto 0);
g_f6_xamcap : std_logic_vector(255 downto 0);
g_f7_adem : std_logic_vector( 31 downto 0);
g_f7_amcap : std_logic_vector( 63 downto 0);
g_f7_xamcap : std_logic_vector(255 downto 0)
); );
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
...@@ -121,7 +148,7 @@ entity VME_bus is ...@@ -121,7 +148,7 @@ entity VME_bus is
stall_i : in std_logic; stall_i : in std_logic;
--CR/CSR space signals: --CR/CSR space signals:
CRAMaddr_o : out std_logic_vector(f_log2_size(g_cram_size)-1 downto 0); CRAMaddr_o : out std_logic_vector(f_log2_size(f_size(g_beg_cram, g_end_cram))-1 downto 0);
CRAMdata_o : out std_logic_vector(7 downto 0); CRAMdata_o : out std_logic_vector(7 downto 0);
CRAMdata_i : in std_logic_vector(7 downto 0); CRAMdata_i : in std_logic_vector(7 downto 0);
CRAMwea_o : out std_logic; CRAMwea_o : out std_logic;
...@@ -244,17 +271,6 @@ architecture RTL of VME_bus is ...@@ -244,17 +271,6 @@ architecture RTL of VME_bus is
signal s_CRdataIn : std_logic_vector(7 downto 0); -- CR data bus signal s_CRdataIn : std_logic_vector(7 downto 0); -- CR data bus
signal s_CRdataIn1 : std_logic_vector(7 downto 0); -- signal s_CRdataIn1 : std_logic_vector(7 downto 0); --
signal s_CRAMdataIn : std_logic_vector(7 downto 0); -- CRAM data bus signal s_CRAMdataIn : std_logic_vector(7 downto 0); -- CRAM data bus
signal s_FUNC_ADEM : t_FUNC_32b_array_std;
signal s_FUNC_AMCAP : t_FUNC_64b_array_std;
signal s_FUNC_XAMCAP : t_FUNC_256b_array_std;
-- CR image registers
signal s_BEG_USER_CSR : std_logic_vector(23 downto 0);
signal s_END_USER_CSR : std_logic_vector(23 downto 0);
signal s_BEG_USER_CR : std_logic_vector(23 downto 0);
signal s_END_USER_CR : std_logic_vector(23 downto 0);
signal s_BEG_CRAM : std_logic_vector(23 downto 0);
signal s_END_CRAM : std_logic_vector(23 downto 0);
-- Error signals -- Error signals
signal s_BERRcondition : std_logic; -- Condition for asserting BERR signal s_BERRcondition : std_logic; -- Condition for asserting BERR
...@@ -262,9 +278,6 @@ architecture RTL of VME_bus is ...@@ -262,9 +278,6 @@ architecture RTL of VME_bus is
signal s_rty1 : std_logic; signal s_rty1 : std_logic;
-- Initialization signals -- Initialization signals
signal s_initInProgress : std_logic; -- The initialization is in progress
signal s_initReadCounter : unsigned(8 downto 0); -- Counts read operations
signal s_initReadCounter1 : std_logic_vector(8 downto 0);
signal s_CRaddr : unsigned(18 downto 0); signal s_CRaddr : unsigned(18 downto 0);
signal s_prev_VME_AS_n : std_logic; signal s_prev_VME_AS_n : std_logic;
...@@ -953,13 +966,11 @@ begin ...@@ -953,13 +966,11 @@ begin
when s_mainFSMreset = '0' when s_mainFSMreset = '0'
else (others => '0'); else (others => '0');
s_CRaddr <= s_CrCsrOffsetAddr s_CRaddr <= s_CrCsrOffsetAddr;
when s_initInProgress = '0'
else resize(s_initReadCounter, s_CRaddr'length);
CRaddr_o <= std_logic_vector(s_CRaddr(11 downto 0)); CRaddr_o <= std_logic_vector(s_CRaddr(11 downto 0));
CRAMaddr_o <= std_logic_vector(resize(s_CrCsrOffsetAddr - unsigned(s_BEG_CRAM(18 downto 0)), CRAMaddr_o <= std_logic_vector(resize(s_CrCsrOffsetAddr - unsigned(g_beg_cram(18 downto 0)),
f_log2_size(g_cram_size))); f_log2_size(f_size(g_beg_cram, g_end_cram))));
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Data Handler Process -- Data Handler Process
...@@ -1195,7 +1206,6 @@ begin ...@@ -1195,7 +1206,6 @@ begin
mainFSMreset => s_mainFSMreset, mainFSMreset => s_mainFSMreset,
decode => s_decode, decode => s_decode,
ModuleEnable => ModuleEnable, ModuleEnable => ModuleEnable,
InitInProgress => s_initInProgress,
Addr => std_logic_vector(s_locAddr), Addr => std_logic_vector(s_locAddr),
Ader0 => Ader0, Ader0 => Ader0,
Ader1 => Ader1, Ader1 => Ader1,
...@@ -1205,30 +1215,30 @@ begin ...@@ -1205,30 +1215,30 @@ begin
Ader5 => Ader5, Ader5 => Ader5,
Ader6 => Ader6, Ader6 => Ader6,
Ader7 => Ader7, Ader7 => Ader7,
Adem0 => s_FUNC_ADEM(0), Adem0 => g_f0_adem,
Adem1 => s_FUNC_ADEM(1), Adem1 => g_f1_adem,
Adem2 => s_FUNC_ADEM(2), Adem2 => g_f2_adem,
Adem3 => s_FUNC_ADEM(3), Adem3 => g_f3_adem,
Adem4 => s_FUNC_ADEM(4), Adem4 => g_f4_adem,
Adem5 => s_FUNC_ADEM(5), Adem5 => g_f5_adem,
Adem6 => s_FUNC_ADEM(6), Adem6 => g_f6_adem,
Adem7 => s_FUNC_ADEM(7), Adem7 => g_f7_adem,
AmCap0 => s_FUNC_AMCAP(0), AmCap0 => g_f0_amcap,
AmCap1 => s_FUNC_AMCAP(1), AmCap1 => g_f1_amcap,
AmCap2 => s_FUNC_AMCAP(2), AmCap2 => g_f2_amcap,
AmCap3 => s_FUNC_AMCAP(3), AmCap3 => g_f3_amcap,
AmCap4 => s_FUNC_AMCAP(4), AmCap4 => g_f4_amcap,
AmCap5 => s_FUNC_AMCAP(5), AmCap5 => g_f5_amcap,
AmCap6 => s_FUNC_AMCAP(6), AmCap6 => g_f6_amcap,
AmCap7 => s_FUNC_AMCAP(7), AmCap7 => g_f7_amcap,
XAmCap0 => s_FUNC_XAMCAP(0), XAmCap0 => g_f0_xamcap,
XAmCap1 => s_FUNC_XAMCAP(1), XAmCap1 => g_f1_xamcap,
XAmCap2 => s_FUNC_XAMCAP(2), XAmCap2 => g_f2_xamcap,
XAmCap3 => s_FUNC_XAMCAP(3), XAmCap3 => g_f3_xamcap,
XAmCap4 => s_FUNC_XAMCAP(4), XAmCap4 => g_f4_xamcap,
XAmCap5 => s_FUNC_XAMCAP(5), XAmCap5 => g_f5_xamcap,
XAmCap6 => s_FUNC_XAMCAP(6), XAmCap6 => g_f6_xamcap,
XAmCap7 => s_FUNC_XAMCAP(7), XAmCap7 => g_f7_xamcap,
Am => s_AMlatched, Am => s_AMlatched,
XAm => std_logic_vector(s_XAM), XAm => std_logic_vector(s_XAM),
BAR_i => BAR_i, BAR_i => BAR_i,
...@@ -1249,24 +1259,24 @@ begin ...@@ -1249,24 +1259,24 @@ begin
s_locAddr(18 downto 0) <= x"7FFFF" and s_locAddr(18 downto 0) <= x"7FFFF" and
s_locAddr(18 downto 0) >= x"7FC00" s_locAddr(18 downto 0) >= x"7FC00"
) xor ( ) xor (
s_locAddr(18 downto 0) >= unsigned(s_BEG_USER_CSR(18 downto 0)) and s_locAddr(18 downto 0) >= unsigned(g_beg_user_csr(18 downto 0)) and
s_locAddr(18 downto 0) <= unsigned(s_END_USER_CSR(18 downto 0)) and s_locAddr(18 downto 0) <= unsigned(g_end_user_csr(18 downto 0)) and
unsigned(s_BEG_USER_CSR) < unsigned(s_END_USER_CSR) unsigned(g_beg_user_csr) < unsigned(g_end_user_csr)
) else '0'; ) else '0';
s_CRaddressed <= '1' when ( s_CRaddressed <= '1' when (
s_locAddr(18 downto 0) <= x"00FFF" and s_locAddr(18 downto 0) <= x"00FFF" and
s_locAddr(18 downto 0) >= x"00000" s_locAddr(18 downto 0) >= x"00000"
) xor ( ) xor (
s_locAddr(18 downto 0) >= unsigned(s_BEG_USER_CR(18 downto 0)) and s_locAddr(18 downto 0) >= unsigned(g_beg_user_cr(18 downto 0)) and
s_locAddr(18 downto 0) <= unsigned(s_END_USER_CR(18 downto 0)) and s_locAddr(18 downto 0) <= unsigned(g_end_user_cr(18 downto 0)) and
unsigned(s_BEG_USER_CR) < unsigned(s_END_USER_CR) unsigned(g_beg_user_cr) < unsigned(g_end_user_cr)
) else '0'; ) else '0';
s_CRAMaddressed <= '1' when ( s_CRAMaddressed <= '1' when (
s_locAddr(18 downto 0) >= unsigned(s_BEG_CRAM(18 downto 0)) and s_locAddr(18 downto 0) >= unsigned(g_beg_cram(18 downto 0)) and
s_locAddr(18 downto 0) <= unsigned(s_END_CRAM(18 downto 0)) and s_locAddr(18 downto 0) <= unsigned(g_end_cram(18 downto 0)) and
unsigned(s_BEG_CRAM) < unsigned(s_END_CRAM) unsigned(g_beg_cram) < unsigned(g_end_cram)
) else '0'; ) else '0';
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -1328,53 +1338,6 @@ begin ...@@ -1328,53 +1338,6 @@ begin
end if; end if;
end process; end process;
------------------------------------------------------------------------------
-- Initialization
------------------------------------------------------------------------------
-- Initialization procedure (about 8800 ns)
-- Read important CR data (like FUNC_ADEMs etc.) and store it locally
s_initReadCounter <= unsigned(s_initReadCounter1);
Inst_VME_Init : VME_Init
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
CRAddr_i => std_logic_vector(s_CRaddr),
CRdata_i => CRdata_i,
InitReadCount_o => s_initReadCounter1,
InitInProgress_o => s_initInProgress,
BEG_USR_CR_o => s_BEG_USER_CR,
END_USR_CR_o => s_END_USER_CR,
BEG_USR_CSR_o => s_BEG_USER_CSR,
END_USR_CSR_o => s_END_USER_CSR,
BEG_CRAM_o => s_BEG_CRAM,
END_CRAM_o => s_END_CRAM,
FUNC0_ADEM_o => s_FUNC_ADEM(0),
FUNC1_ADEM_o => s_FUNC_ADEM(1),
FUNC2_ADEM_o => s_FUNC_ADEM(2),
FUNC3_ADEM_o => s_FUNC_ADEM(3),
FUNC4_ADEM_o => s_FUNC_ADEM(4),
FUNC5_ADEM_o => s_FUNC_ADEM(5),
FUNC6_ADEM_o => s_FUNC_ADEM(6),
FUNC7_ADEM_o => s_FUNC_ADEM(7),
FUNC0_AMCAP_o => s_FUNC_AMCAP(0),
FUNC1_AMCAP_o => s_FUNC_AMCAP(1),
FUNC2_AMCAP_o => s_FUNC_AMCAP(2),
FUNC3_AMCAP_o => s_FUNC_AMCAP(3),
FUNC4_AMCAP_o => s_FUNC_AMCAP(4),
FUNC5_AMCAP_o => s_FUNC_AMCAP(5),
FUNC6_AMCAP_o => s_FUNC_AMCAP(6),
FUNC7_AMCAP_o => s_FUNC_AMCAP(7),
FUNC0_XAMCAP_o => s_FUNC_XAMCAP(0),
FUNC1_XAMCAP_o => s_FUNC_XAMCAP(1),
FUNC2_XAMCAP_o => s_FUNC_XAMCAP(2),
FUNC3_XAMCAP_o => s_FUNC_XAMCAP(3),
FUNC4_XAMCAP_o => s_FUNC_XAMCAP(4),
FUNC5_XAMCAP_o => s_FUNC_XAMCAP(5),
FUNC6_XAMCAP_o => s_FUNC_XAMCAP(6),
FUNC7_XAMCAP_o => s_FUNC_XAMCAP(7)
);
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Edge Detection and Sampling -- Edge Detection and Sampling
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 781e4153
...@@ -184,32 +184,6 @@ package vme64x_pack is ...@@ -184,32 +184,6 @@ package vme64x_pack is
constant WB32bits : integer := FUNC0_ADER_3 - 12; constant WB32bits : integer := FUNC0_ADER_3 - 12;
constant Endian : integer := FUNC0_ADER_3 - 4; constant Endian : integer := FUNC0_ADER_3 - 4;
-- Initialization CR:
constant BEG_USER_CR : integer := 1;
constant END_USER_CR : integer := 2;
constant BEG_CRAM : integer := 3;
constant END_CRAM : integer := 4;
constant BEG_USER_CSR : integer := 5;
constant END_USER_CSR : integer := 6;
constant FUNC_AMCAP : integer := 7;
constant FUNC_XAMCAP : integer := 8;
constant FUNC_ADEM : integer := 9;
constant c_CRinitAddr : t_cr_add_table(BEG_USER_CR to FUNC_ADEM) := (
BEG_USER_CR => (add => 16#020#, len => 3),
END_USER_CR => (add => 16#023#, len => 3),
BEG_CRAM => (add => 16#26#, len => 3),
END_CRAM => (add => 16#29#, len => 3),
BEG_USER_CSR => (add => 16#02C#, len => 3),
END_USER_CSR => (add => 16#02F#, len => 3),
FUNC_AMCAP => (add => 16#048#, len => 64),
FUNC_XAMCAP => (add => 16#088#, len => 256),
FUNC_ADEM => (add => 16#188#, len => 32)
);
-- Main Finite State machine signals default: -- Main Finite State machine signals default:
-- When the S_FPGA detects the magic sequency, it erases the A_FPGA so -- When the S_FPGA detects the magic sequency, it erases the A_FPGA so
-- I don't need to drive the s_dtackOE, s_dataOE, s_addrOE, s_addrDir, s_dataDir -- I don't need to drive the s_dtackOE, s_dataOE, s_addrOE, s_addrDir, s_dataDir
...@@ -415,15 +389,6 @@ package vme64x_pack is ...@@ -415,15 +389,6 @@ package vme64x_pack is
type t_FUNC_256b_array is type t_FUNC_256b_array is
array (0 to 7) of unsigned(255 downto 0); -- XAMCAP register array array (0 to 7) of unsigned(255 downto 0); -- XAMCAP register array
type t_FUNC_32b_array_std is
array (0 to 7) of std_logic_vector(31 downto 0); -- ADER register array
type t_FUNC_64b_array_std is
array (0 to 7) of std_logic_vector(63 downto 0); -- AMCAP register array
type t_FUNC_256b_array_std is
array (0 to 7) of std_logic_vector(255 downto 0); -- XAMCAP register array
type t_csr_array is type t_csr_array is
array(BAR downto WB32bits) of unsigned(7 downto 0); array(BAR downto WB32bits) of unsigned(7 downto 0);
...@@ -599,7 +564,36 @@ package vme64x_pack is ...@@ -599,7 +564,36 @@ package vme64x_pack is
g_clock : integer; g_clock : integer;
g_wb_data_width : integer; g_wb_data_width : integer;
g_wb_addr_width : integer; g_wb_addr_width : integer;
g_cram_size : integer g_beg_user_cr : std_logic_vector( 23 downto 0);
g_end_user_cr : std_logic_vector( 23 downto 0);
g_beg_cram : std_logic_vector( 23 downto 0);
g_end_cram : std_logic_vector( 23 downto 0);
g_beg_user_csr : std_logic_vector( 23 downto 0);
g_end_user_csr : std_logic_vector( 23 downto 0);
g_f0_adem : std_logic_vector( 31 downto 0);
g_f0_amcap : std_logic_vector( 63 downto 0);
g_f0_xamcap : std_logic_vector(255 downto 0);
g_f1_adem : std_logic_vector( 31 downto 0);
g_f1_amcap : std_logic_vector( 63 downto 0);
g_f1_xamcap : std_logic_vector(255 downto 0);
g_f2_adem : std_logic_vector( 31 downto 0);
g_f2_amcap : std_logic_vector( 63 downto 0);
g_f2_xamcap : std_logic_vector(255 downto 0);
g_f3_adem : std_logic_vector( 31 downto 0);
g_f3_amcap : std_logic_vector( 63 downto 0);
g_f3_xamcap : std_logic_vector(255 downto 0);
g_f4_adem : std_logic_vector( 31 downto 0);
g_f4_amcap : std_logic_vector( 63 downto 0);
g_f4_xamcap : std_logic_vector(255 downto 0);
g_f5_adem : std_logic_vector( 31 downto 0);
g_f5_amcap : std_logic_vector( 63 downto 0);
g_f5_xamcap : std_logic_vector(255 downto 0);
g_f6_adem : std_logic_vector( 31 downto 0);
g_f6_amcap : std_logic_vector( 63 downto 0);
g_f6_xamcap : std_logic_vector(255 downto 0);
g_f7_adem : std_logic_vector( 31 downto 0);
g_f7_amcap : std_logic_vector( 63 downto 0);
g_f7_xamcap : std_logic_vector(255 downto 0)
); );
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
...@@ -654,7 +648,7 @@ package vme64x_pack is ...@@ -654,7 +648,7 @@ package vme64x_pack is
wbSel_o : out std_logic_vector(g_wb_data_width/8-1 downto 0); wbSel_o : out std_logic_vector(g_wb_data_width/8-1 downto 0);
RW_o : out std_logic; RW_o : out std_logic;
cyc_o : out std_logic; cyc_o : out std_logic;
CRAMaddr_o : out std_logic_vector(f_log2_size(g_cram_size)-1 downto 0); CRAMaddr_o : out std_logic_vector(f_log2_size(f_size(g_beg_cram, g_end_cram))-1 downto 0);
CRAMdata_o : out std_logic_vector(7 downto 0); CRAMdata_o : out std_logic_vector(7 downto 0);
CRAMwea_o : out std_logic; CRAMwea_o : out std_logic;
CRaddr_o : out std_logic_vector(11 downto 0); CRaddr_o : out std_logic_vector(11 downto 0);
...@@ -672,7 +666,6 @@ package vme64x_pack is ...@@ -672,7 +666,6 @@ package vme64x_pack is
mainFSMreset : in std_logic; mainFSMreset : in std_logic;
decode : in std_logic; decode : in std_logic;
ModuleEnable : in std_logic; ModuleEnable : in std_logic;
InitInProgress : in std_logic;
Addr : in std_logic_vector(63 downto 0); Addr : in std_logic_vector(63 downto 0);
Ader0 : in std_logic_vector(31 downto 0); Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0); Ader1 : in std_logic_vector(31 downto 0);
...@@ -764,8 +757,8 @@ package vme64x_pack is ...@@ -764,8 +757,8 @@ package vme64x_pack is
CrCsrOffsetAddr : in std_logic_vector(18 downto 0); CrCsrOffsetAddr : in std_logic_vector(18 downto 0);
VME_GA_oversampled : in std_logic_vector(5 downto 0); VME_GA_oversampled : in std_logic_vector(5 downto 0);
locDataIn : in std_logic_vector(7 downto 0); locDataIn : in std_logic_vector(7 downto 0);
err_flag : in std_logic;
CR_data : out std_logic_vector(7 downto 0); CR_data : out std_logic_vector(7 downto 0);
err_flag : in std_logic;
CRAM_data_o : out std_logic_vector(7 downto 0); CRAM_data_o : out std_logic_vector(7 downto 0);
reset_flag : out std_logic; reset_flag : out std_logic;
CSRdata : out std_logic_vector(7 downto 0); CSRdata : out std_logic_vector(7 downto 0);
...@@ -858,47 +851,6 @@ package vme64x_pack is ...@@ -858,47 +851,6 @@ package vme64x_pack is
); );
end component VME_Wb_master; end component VME_Wb_master;
component VME_Init is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
CRAddr_i : in std_logic_vector(18 downto 0);
CRdata_i : in std_logic_vector(7 downto 0);
InitReadCount_o : out std_logic_vector(8 downto 0);
InitInProgress_o : out std_logic;
BEG_USR_CR_o : out std_logic_vector(23 downto 0);
END_USR_CR_o : out std_logic_vector(23 downto 0);
BEG_USR_CSR_o : out std_logic_vector(23 downto 0);
END_USR_CSR_o : out std_logic_vector(23 downto 0);
BEG_CRAM_o : out std_logic_vector(23 downto 0);
END_CRAM_o : out std_logic_vector(23 downto 0);
FUNC0_ADEM_o : out std_logic_vector(31 downto 0);
FUNC1_ADEM_o : out std_logic_vector(31 downto 0);
FUNC2_ADEM_o : out std_logic_vector(31 downto 0);
FUNC3_ADEM_o : out std_logic_vector(31 downto 0);
FUNC4_ADEM_o : out std_logic_vector(31 downto 0);
FUNC5_ADEM_o : out std_logic_vector(31 downto 0);
FUNC6_ADEM_o : out std_logic_vector(31 downto 0);
FUNC7_ADEM_o : out std_logic_vector(31 downto 0);
FUNC0_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC1_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC2_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC3_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC4_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC5_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC6_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC7_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC0_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC1_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC2_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC3_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC4_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC5_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC6_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC7_XAMCAP_o : out std_logic_vector(255 downto 0)
);
end component VME_Init;
component VME_swapper is component VME_swapper is
port ( port (
d_i : in std_logic_vector(63 downto 0); d_i : in std_logic_vector(63 downto 0);
......
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