Remove f_div8() function

The f_div8(n) function has been replaced by n/8 as this is simpler and more clear. Signed-off-by: Tom Levens <tom.levens@cern.ch>

Remove f_div8() function
The f_div8(n) function has been replaced by n/8 as this is simpler and more clear. Signed-off-by: Tom Levens <tom.levens@cern.ch>
6994f35b · Tom Levens · af4ec2d0 · 6994f35b · 6994f35b · 6994f35b
Commit 6994f35b authored Jan 10, 2017 by Tom Levens
5 changed files
--- a/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+++ b/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
@@ -192,7 +192,7 @@ entity VME64xCore_Top is
    CYC_o   : out std_logic;
    ERR_i   : in  std_logic;
    RTY_i   : in  std_logic;
-    SEL_o   : out std_logic_vector(f_div8(g_wb_data_width)-1 downto 0);
+    SEL_o   : out std_logic_vector(g_wb_data_width/8-1 downto 0);
    STB_o   : out std_logic;
    ACK_i   : in  std_logic;
    WE_o    : out std_logic;

--- a/hdl/vme64x-core/rtl/VME_Wb_master.vhd
+++ b/hdl/vme64x-core/rtl/VME_Wb_master.vhd
@@ -99,7 +99,7 @@ entity VME_Wb_master is
    wbData_i        : in  std_logic_vector(g_wb_data_width-1 downto 0);
    locAddr_o       : out std_logic_vector(g_wb_addr_width-1 downto 0);
    memAckWB_i      : in  std_logic;
-    WbSel_o         : out std_logic_vector(f_div8(g_wb_data_width)-1 downto 0);
+    WbSel_o         : out std_logic_vector(g_wb_data_width/8-1 downto 0);
    RW_o            : out std_logic
  );
 end VME_Wb_master;

--- a/hdl/vme64x-core/rtl/VME_bus.vhd
+++ b/hdl/vme64x-core/rtl/VME_bus.vhd
@@ -113,7 +113,7 @@ entity VME_bus is
    wbData_o        : out std_logic_vector(g_wb_data_width-1 downto 0);
    wbData_i        : in  std_logic_vector(g_wb_data_width-1 downto 0);
    locAddr_o       : out std_logic_vector(g_wb_addr_width-1 downto 0);
-    wbSel_o         : out std_logic_vector(f_div8(g_wb_data_width)-1 downto 0);
+    wbSel_o         : out std_logic_vector(g_wb_data_width/8-1 downto 0);
    RW_o            : out std_logic;
    cyc_o           : out std_logic;
    err_i           : in  std_logic;

--- a/hdl/vme64x-core/rtl/vme64x_pack.vhd
+++ b/hdl/vme64x-core/rtl/vme64x_pack.vhd
@@ -456,10 +456,6 @@ package vme64x_pack is
  -- Functions
  ------------------------------------------------------------------------------

-  function f_div8 (
-    width : integer
-  ) return integer;
-
  function f_log2_size (
    A : natural
  ) return natural;
@@ -537,7 +533,7 @@ package vme64x_pack is
      memReq_o        : out std_logic;
      wbData_o        : out std_logic_vector(g_wb_data_width-1 downto 0);
      locAddr_o       : out std_logic_vector(g_wb_addr_width-1 downto 0);
-      wbSel_o         : out std_logic_vector(f_div8(g_wb_data_width)-1 downto 0);
+      wbSel_o         : out std_logic_vector(g_wb_data_width/8-1 downto 0);
      RW_o            : out std_logic;
      cyc_o           : out std_logic;
      CRAMaddr_o      : out std_logic_vector(f_log2_size(g_cram_size)-1 downto 0);
@@ -743,7 +739,7 @@ package vme64x_pack is
      memReq_o        : out std_logic;
      WBdata_o        : out std_logic_vector(g_wb_data_width-1 downto 0);
      locAddr_o       : out std_logic_vector(g_wb_addr_width-1 downto 0);
-      WbSel_o         : out std_logic_vector(f_div8(g_wb_data_width)-1 downto 0);
+      WbSel_o         : out std_logic_vector(g_wb_data_width/8-1 downto 0);
      RW_o            : out std_logic
    );
  end component VME_Wb_master;
@@ -931,16 +927,6 @@ end vme64x_pack;

 package body vme64x_pack is

-  function f_div8 (width : integer) return integer is
-  begin
-    for I in 1 to 8 loop
-      if (8*I >= width) then
-        return(I);
-      end if;
-    end loop;
-    return -1;
-  end function f_div8;
-
  function f_log2_size (A : natural) return natural is
  begin
    for I in 1 to 64 loop               -- Works for up to 64 bits

--- a/hdl/vme64x-core/rtl/xvme64x_core.vhd
+++ b/hdl/vme64x-core/rtl/xvme64x_core.vhd
@@ -125,7 +125,7 @@ architecture wrapper of xvme64x_core is
      CYC_o           : out std_logic;
      ERR_i           : in  std_logic;
      RTY_i           : in  std_logic;
-      SEL_o           : out std_logic_vector(f_div8(g_wb_data_width)-1 downto 0);
+      SEL_o           : out std_logic_vector(g_wb_data_width/8-1 downto 0);
      STB_o           : out std_logic;
      ACK_i           : in  std_logic;
      WE_o            : out std_logic;