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Commit 4e89e511 authored by dpedrett's avatar dpedrett
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Top Level used to test the vme64x core on the VFC board 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@170 665b4545-5c6b-4c24-801b-41150b02b44b
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hdl/boards/vfc/rtl/IRQ_Generator_Top.vhd 0 → 100644
View file @ 4e89e511
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: IRQ_Generator_Top.vhd
--______________________________________________________________________
-- Description: This block implement a IRQ_Generator both WB 32 or 64
-- data transfer bus width compatible.
-- Block diagram:
-- ____________________________________________
-- | |
-- | |
-- | __________ ______________ |
-- | | WB | | INT_COUNT | |
-- | | LOGIC | |______________| |
-- W | | | ______________ |
-- B | | | | FREQ | |
-- | | | |______________| |
-- S | | | ______________ |
-- I | | | | | |
-- G | | | | | |
-- N | | | | IRQ | |
-- A | | | |Generator.vhd | |
-- L | | | | | |
-- S | | | | | |
-- | | | | | |
-- | |__________| | | |
-- | | | |
-- | |______________| |
-- | |
-- | |
-- |____________________________________________|
--
-- INT_COUNT --> address: 0x000
-- FREQ --> address: 0x004
-- IRQ Generator: this component sends an Interrupt request (pulse) to the
-- IRQ Controller --> Necessary to test the board.
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity IRQ_Generator_Top is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
);
port ( -- IRQ_Generator
clk_i : in std_logic;
rst_i : in std_logic;
Int_Ack_i : in std_logic;
Int_Req_o : out std_logic;
-- wb slave side
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector (g_addr_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_width) - 1 downto 0);
we_i : in std_logic;
dat_i : in std_logic_vector (g_width - 1 downto 0);
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector (g_width - 1 downto 0)
);
end IRQ_Generator_Top;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of IRQ_Generator_Top is
signal s_rst : std_logic;
signal s_INT_COUNT : std_logic_vector(31 downto 0);
signal s_FREQ : std_logic_vector(31 downto 0);
signal s_Int_Count_o1 : std_logic_vector(31 downto 0);
signal s_Int_Count_o : std_logic_vector(31 downto 0);
signal s_Read_IntCount : std_logic;
signal s_data : std_logic_vector(31 downto 0);
signal s_data_f : std_logic_vector(31 downto 0);
signal s_data_o : std_logic_vector(g_width - 1 downto 0);
signal s_IntCount_sel : std_logic;
signal s_Freq_sel : std_logic;
signal s_wea : std_logic;
signal s_stall : std_logic;
signal s_ack : std_logic;
signal s_en_Freq : std_logic;
component IRQ_generator is
port(
clk_i : in std_logic;
reset : in std_logic;
Freq : in std_logic_vector(31 downto 0);
Int_Count_i : in std_logic_vector(31 downto 0);
Read_Int_Count : in std_logic;
INT_ack : in std_logic;
IRQ_o : out std_logic;
Int_Count_o : out std_logic_vector(31 downto 0)
);
end component IRQ_generator;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
s_rst <= not(rst_i);
s_wea <= we_i and cyc_i and stb_i and (not s_stall);
s_Int_Count_o1 <= s_data when (s_IntCount_sel = '1' and s_wea = '1')
else s_Int_Count_o;
s_Read_IntCount <= '1' when s_IntCount_sel = '1' and we_i = '0' and s_ack = '1'
else '0';
s_en_Freq <= '1' when (s_Freq_sel = '1' and s_wea = '1') else '0';
------------------------------------------------------------------------------------
-- The INT_COUNT register and the INT_RATE register should be write/read both when
-- the WB data bus is 32 or 64 bit width, so the following processes have been
-- added:
gen64 : if (g_width = 64) generate
s_data <= dat_i(63 downto 32);
s_data_f <= dat_i(31 downto 0);
s_data_o <= s_INT_COUNT & s_FREQ;
s_IntCount_sel <= '1' when sel_i = "11110000" and unsigned(adr_i) = 0 else
'0' ;
s_Freq_sel <= '1' when sel_i = "00001111" and unsigned(adr_i) = 0 else
'0';
end generate gen64;
gen32 : if (g_width = 32) generate
s_data <= dat_i;
s_data_f <= dat_i;
s_data_o <= s_INT_COUNT when s_IntCount_sel = '1' else
s_FREQ when s_Freq_sel = '1' else
(others => '0');
s_IntCount_sel <= '1' when unsigned(adr_i) = 0 else
'0' ;
s_Freq_sel <= '1' when unsigned(adr_i) = 1 else
'0';
end generate gen32;
---------------------------------------------------------------
-- this process generate the ack; PIPELINED mode!
process(clk_i)
begin
if(rising_edge(clk_i)) then
if(s_rst = '0') then
s_ack <= '0';
else
s_ack <= cyc_i and stb_i and (not s_stall) ;
end if;
end if;
end process;
----------------------------------------------------------------
-- stall handler
process(clk_i)
begin
if(rising_edge(clk_i)) then
if(s_rst = '0') or s_ack = '1' then
s_stall <= '1';
elsif cyc_i = '1' then
s_stall <= '0';
end if;
end if;
end process;
-- Reg INT_COUNT
INT_COUNT : Reg32bit
port map(
reset => s_rst,
enable => '1',
di => s_Int_Count_o1,
do => s_INT_COUNT,
clk_i => clk_i
);
-- Reg FREQ
FREQ : Reg32bit
port map(
reset => s_rst,
enable => s_en_Freq,
di => s_data_f,
do => s_FREQ,
clk_i => clk_i
);
-- IRQ Generator
Inst_IRQ_generator: IRQ_generator port map(
clk_i => clk_i,
reset => s_rst,
Freq => s_FREQ,
Int_Count_i => s_INT_COUNT,
Read_Int_Count => s_Read_IntCount,
INT_ack => Int_Ack_i,
IRQ_o => Int_Req_o,
Int_Count_o => s_Int_Count_o
);
------------------------------------------------------------------
stall_o <= s_stall;
ack_o <= s_ack;
err_o <= '0';
rty_o <= '0';
dat_o <= s_data_o;
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/boards/vfc/rtl/IRQ_generator.vhd
View file @ 4e89e511
......@@ -57,11 +57,12 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......@@ -75,9 +76,12 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity IRQ_generator is
Port ( clk_i : in std_logic;
port ( clk_i : in std_logic;
reset : in std_logic;
Freq : in std_logic_vector (31 downto 0);
Int_Count_i : in std_logic_vector (31 downto 0);
......@@ -86,8 +90,11 @@ entity IRQ_generator is
IRQ_o : out std_logic;
Int_Count_o : out std_logic_vector (31 downto 0));
end IRQ_generator;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of IRQ_generator is
type t_FSM is (IDLE, CHECK, INCR, IRQ, WAIT_INT_ACK, WAIT_RD);
signal s_en_int : std_logic;
signal currs, nexts : t_FSM;
......@@ -101,16 +108,18 @@ signal s_incr : std_logic;
signal s_gen_irq : std_logic;
signal s_count0 : std_logic;
signal s_Freq : std_logic_vector(31 downto 0);
--===========================================================================
-- Architecture begin
--===========================================================================
begin
-- In/Out sample
RDinputSample : entity work.DoubleSigInputSample
RDinputSample : DoubleSigInputSample
port map(
sig_i => Read_Int_Count,
sig_o => s_Rd_Int_Count_delayed,
clk_i => clk_i
);
IRQOutputSample : entity work.FlipFlopD
IRQOutputSample : FlipFlopD
port map(
sig_i => s_IRQ_o,
sig_o => IRQ_o,
......@@ -263,6 +272,7 @@ begin
end process;
-- Update outputs
-- Moore FSM
process(currs)
begin
case currs is
......@@ -294,4 +304,6 @@ end process;
Int_Count_o <= std_logic_vector(s_count_int);
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/boards/vfc/rtl/TOP_LEVEL.vhd
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hdl/boards/vfc/rtl/WB_Bridge.vhd 0 → 100644
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--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: WB_Bridge.vhd
--_____________________________________________________________________________
-- Description: Insert this block between the vme64x core and your WB Application
-- if you want use the Interrupter.
-- Indeed this component acts as a bridge between the vme64x core and your WB
-- Application, and implements the IRQ Generator that sends the Interrupt request
-- to the IRQ_Controller located in the vme64x core.
-- Remember that:
-- INT_COUNT register --> 0x00
-- INT_RATE register --> 0x04
-- These two address (byte address) are reserved; don't use these to access
-- your WB memory!
--
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity WB_Bridge is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
);
Port ( clk_i : in std_logic;
rst_i : in std_logic;
Int_Ack_i : in std_logic;
Int_Req_o : out std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector (g_addr_width - 1 downto 0);
dat_i : in std_logic_vector (g_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_width) - 1 downto 0);
we_i : in std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector (g_width - 1 downto 0);
m_cyc_o : out std_logic;
m_stb_o : out std_logic;
m_adr_o : out std_logic_vector (g_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector (g_width - 1 downto 0);
m_sel_o : out std_logic_vector (f_div8(g_width) - 1 downto 0);
m_we_o : out std_logic;
m_ack_i : in std_logic;
m_err_i : in std_logic;
m_stall_i : in std_logic;
m_rty_i : in std_logic;
m_dat_i : in std_logic_vector (g_width - 1 downto 0));
end WB_Bridge;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of WB_Bridge is
signal s_cyc : std_logic;
signal s_m_cyc : std_logic;
signal s_stb : std_logic;
signal s_m_stb : std_logic;
signal s_WbAppl : std_logic;
signal s_IRQGen : std_logic;
signal s_ack_gen : std_logic;
signal s_err_gen : std_logic;
signal s_rty_gen : std_logic;
signal s_stall_gen : std_logic;
signal s_data_o_gen : std_logic_vector(g_width - 1 downto 0);
component IRQ_Generator_Top is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
Int_Ack_i : in std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector(g_addr_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_width) - 1 downto 0);
we_i : in std_logic;
dat_i : in std_logic_vector(g_width - 1 downto 0);
Int_Req_o : out std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector(g_width - 1 downto 0)
);
end component IRQ_Generator_Top;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
---------------------------------------------------------------------
-- check if the IRQ Generator is addressed (0x00 or 0x04).
-- if not s_WbAppl is '1' and the component work as a bridge
-- between the vme64x core and the Wb Application
genIRQGen64 : if (g_width = 64) generate
s_IRQGen <= '1' when (unsigned(adr_i) = 0) else '0';
end generate genIRQGen64;
genIRQGen32 : if (g_width = 32) generate
s_IRQGen <= '1' when unsigned(adr_i) = 0 or
unsigned(adr_i) = 1 else '0';
end generate genIRQGen32;
s_WbAppl <= not s_IRQGen;
---------------------------------------------------------------------
s_cyc <= cyc_i and s_IRQGen;
s_stb <= stb_i and s_IRQGen;
s_m_cyc <= cyc_i and s_WbAppl;
s_m_stb <= stb_i and s_WbAppl;
----------------------------------------------------------------------
ack_o <= s_ack_gen xor m_ack_i;
err_o <= s_err_gen xor m_err_i;
rty_o <= s_rty_gen xor m_rty_i;
----------------------------------------------------------------------
stall_o <= m_stall_i when s_WbAppl ='1' else
s_stall_gen;
dat_o <= m_dat_i when s_WbAppl ='1' else
s_data_o_gen;
----------------------------------------------------------------------
m_cyc_o <= s_m_cyc;
m_stb_o <= s_m_stb;
m_adr_o <= adr_i;
m_dat_o <= dat_i;
m_sel_o <= sel_i;
m_we_o <= we_i;
----------------------------------------------------------------------
Inst_IRQ_Generator_Top: IRQ_Generator_Top
generic map(g_width => g_width,
g_addr_width => g_addr_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
Int_Ack_i => Int_Ack_i,
Int_Req_o => Int_Req_o,
cyc_i => s_cyc,
stb_i => s_stb,
adr_i => adr_i,
sel_i => sel_i,
we_i => we_i,
dat_i => dat_i,
ack_o => s_ack_gen,
err_o => s_err_gen,
rty_o => s_rty_gen,
stall_o => s_stall_gen,
dat_o => s_data_o_gen
);
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/boards/vfc/rtl/genram_pkg.vhd 0 → 100644
View file @ 4e89e511
-------------------------------------------------------------------------------
-- Title : Main package file
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : genram_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2011-05-11
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
package genram_pkg is
constant c_SIZE : integer := 256;
function f_log2_size (A : natural) return natural;
-- Single-port synchronous RAM
component generic_spram
generic (
g_data_width : natural ;
g_size : natural := 16 ;
g_with_byte_enable : boolean := false;
g_init_file : string := "";
g_addr_conflict_resolution : string := "read_first") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
we_i : in std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
d_i : in std_logic_vector(g_data_width-1 downto 0);
q_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector(g_data_width/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector(g_data_width/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_empty : boolean := true;
g_with_full : boolean := true;
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
end genram_pkg;
package body genram_pkg is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
end genram_pkg;
hdl/boards/vfc/rtl/ram_8bits.vhd
View file @ 4e89e511
......@@ -9,8 +9,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -29,11 +29,12 @@ use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity ram_8bits is
generic (
size : natural := 256
size : integer := c_SIZE
);
Port ( addr : in std_logic_vector (f_log2_size(size)-1 downto 0);
di : in std_logic_vector (7 downto 0);
......@@ -41,10 +42,15 @@ entity ram_8bits is
we : in std_logic;
clk_i : in std_logic);
end ram_8bits;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of ram_8bits is
type t_ram_type is array(size-1 downto 0) of std_logic_vector(7 downto 0);
signal sram : t_ram_type;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
process (clk_i)
begin
......@@ -56,4 +62,6 @@ process (clk_i)
end if;
end process;
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/boards/vfc/rtl/spram.vhd
View file @ 4e89e511
......@@ -11,8 +11,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -33,12 +33,15 @@ use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity spram is
generic (
-- standard parameters
g_data_width : natural := 64;
g_size : natural := 256;
g_data_width : integer := c_wishbone_data_width;
g_size : integer := c_SIZE;
-- if true, the user can write individual bytes by using bwe_i
g_with_byte_enable : boolean := true; --not used
-- RAM read-on-write conflict resolution. Can be "read_first" (read-then-write)
......@@ -58,15 +61,19 @@ port (
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end spram;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of spram is
constant c_num_bytes : integer := (g_data_width)/8;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
spram: for i in 0 to c_num_bytes-1 generate
ram8bits : entity work.ram_8bits
generic map(g_size)
generic map(size => g_size)
port map(addr => a_i,
di => d_i(8*i+7 downto 8*i),
do => q_o(8*i+7 downto 8*i),
......@@ -76,4 +83,6 @@ begin
end generate;
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/boards/vfc/rtl/wishbone_pkg.vhd 0 → 100755
View file @ 4e89e511
This diff is collapsed.
hdl/boards/vfc/rtl/xwb_dpram.vhd deleted 100755 → 0
View file @ d4659ea1
-------------------------------------------------------------------------------
-- Title : Dual-port RAM for WR core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wrc_dpram.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-15
-- Last update: 2011-09-26
-- Platform : FPGA-generics
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Description:
--
-- Dual port RAM with wishbone interface
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-15 1.0 greg.d Created
-- 2011-06-09 1.01 twlostow Removed unnecessary generics
-- 2011-21-09 1.02 twlostow Struct-ized version
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
entity xwb_dpram is
generic(
g_size : natural := 256;
g_init_file : string := "";
g_must_have_init_file : boolean := false;
g_slave1_interface_mode : t_wishbone_interface_mode;
-- g_slave2_interface_mode : t_wishbone_interface_mode;
g_slave1_granularity : t_wishbone_address_granularity
--g_slave2_granularity : t_wishbone_address_granularity
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
INT_ack : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out
--slave2_i : in t_wishbone_slave_in;
-- slave2_o : out t_wishbone_slave_out
);
end xwb_dpram;
architecture struct of xwb_dpram is
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
signal s_wea : std_logic;
--signal s_web : std_logic;
signal s_bwea : std_logic_vector(c_wishbone_data_width/8-1 downto 0); -- it was: std_logic_vector(3 downto 0);
-- signal s_bweb : std_logic_vector(3 downto 0);
signal slave1_in : t_wishbone_slave_in;
signal slave1_out : t_wishbone_slave_out;
--signal slave2_in : t_wishbone_slave_in;
--signal slave2_out : t_wishbone_slave_out;
signal s_cyc : std_logic;
signal s_stb : std_logic;
COMPONENT IRQ_generator
PORT(
clk_i : IN std_logic;
reset : IN std_logic;
Freq : IN std_logic_vector(31 downto 0);
Int_Count_i : IN std_logic_vector(31 downto 0);
Read_Int_Count : IN std_logic;
INT_ack : IN std_logic;
IRQ_o : OUT std_logic;
Int_Count_o : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
signal s_INT_COUNT : std_logic_vector(31 downto 0);
signal s_FREQ : std_logic_vector(31 downto 0);
signal s_q_o : std_logic_vector(63 downto 0);
signal s_q_o1 : std_logic_vector(63 downto 0);
signal s_en_Freq : std_logic;
signal s_sel_IntCount : std_logic;
--signal s_IRQ : std_logic;
signal s_Int_Count_o : std_logic_vector(31 downto 0);
signal s_Int_Count_o1 : std_logic_vector(31 downto 0);
signal s_Read_IntCount : std_logic;
signal s_rst : std_logic;
signal s_stall : std_logic;
begin
s_rst <= not(rst_n_i);
s_q_o1 <= s_INT_COUNT & s_FREQ;
s_en_Freq <= '1' when (unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0)) = 0 and s_bwea = "00001111") else '0';
s_Int_Count_o1 <= slave1_i.dat(63 downto 32) when (s_bwea = "11110000" and (unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0))) = 0) else s_Int_Count_o;
s_Read_IntCount <= '1' when (slave1_i.we = '0' and slave1_i.sel = "11110000" and (unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0))) = 0 and slave1_out.ack = '1') else '0';
-- Reg INT_COUNT
INT_COUNT : entity work.Reg32bit
port map(
reset => s_rst,
enable => '1',
di => s_Int_Count_o1,
do => s_INT_COUNT,
clk_i => clk_sys_i
);
-- Reg FREQ
FREQ : entity work.Reg32bit
port map(
reset => s_rst,
enable => s_en_Freq,
di => slave1_i.dat(31 downto 0),
do => s_FREQ,
clk_i => clk_sys_i
);
Inst_IRQ_generator: IRQ_generator PORT MAP(
clk_i => clk_sys_i,
reset => s_rst,
Freq => s_FREQ,
Int_Count_i => s_INT_COUNT,
Read_Int_Count => s_Read_IntCount,
INT_ack => INT_ack,
IRQ_o => slave1_o.int,
Int_Count_o => s_Int_Count_o
);
U_DPRAM : entity work.spram
generic map(
-- standard parameters
g_data_width => 64,
g_size => 256,
g_with_byte_enable => true,
g_init_file => "",
g_addr_conflict_resolution => "read_first"
)
port map(
-- rst_n_i => rst_n_i,
clk_i => clk_sys_i,
bwe_i => s_bwea,
-- we_i => s_wea,
a_i => slave1_i.adr(f_log2_size(g_size)-1 downto 0), -- it was slave1_in.adr
d_i => slave1_i.dat, -- it was slave1_in.adr
q_o => s_q_o -- it was slave1_out.dat
);
-- rst_n_i => rst_n_i,
-- Port A
-- clka_i => clk_sys_i,
-- bwea_i => s_bwea,
-- wea_i => s_wea,
-- aa_i => slave1_in.adr(f_log2_size(g_size)-1 downto 0),
-- da_i => slave1_in.dat,
-- qa_o => slave1_out.dat,
-- -- Port B
-- clkb_i => clk_sys_i,
-- bweb_i => s_bweb,
-- web_i => s_web,
-- ab_i => slave2_in.adr(f_log2_size(g_size)-1 downto 0),
-- db_i => slave2_in.dat,
-- qb_o => slave2_out.dat
-- );
-- I know this looks weird, but otherwise ISE generates distributed RAM instead of block
-- RAM
s_bwea <= slave1_i.sel when s_wea = '1' else f_zeros(c_wishbone_data_width/8); --it was slave1_in.sel
-- s_bweb <= slave2_in.sel when s_web = '1' else f_zeros(c_wishbone_data_width/8);
s_wea <= slave1_i.we and slave1_i.cyc and slave1_i.stb and (not s_stall); -- it was slave1_in.we and slave1_in.stb and slave1_in.cyc;
--s_web <= slave2_in.we and slave2_in.stb and slave2_in.cyc;
process(clk_sys_i)
begin
if(rising_edge(clk_sys_i)) then
if(s_rst = '0') then
slave1_out.ack <= '0'; -- it was slave1_out.ack and slave1_in in all the process
-- slave2_out.ack <= '0';
else
if(slave1_out.ack = '1' and g_slave1_interface_mode = CLASSIC) then
slave1_out.ack <= '0';
else
slave1_out.ack <= slave1_i.cyc and slave1_i.stb and (not s_stall) ;
end if;
-- if(slave2_out.ack = '1' and g_slave2_interface_mode = CLASSIC) then
-- slave2_out.ack <= '0';
-- else
-- slave2_out.ack <= slave2_in.cyc and slave2_in.stb;
-- end if;
end if;
end if;
end process;
process(clk_sys_i)
begin
if(rising_edge(clk_sys_i)) then
if(s_rst = '0') or slave1_out.ack = '1' then
s_stall <= '1';
elsif slave1_i.cyc = '1' then
s_stall <= '0';
end if;
end if;
end process;
slave1_o.dat <= s_q_o1 when unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0)) = 0 else s_q_o;
slave1_o.stall <= s_stall;
-- slave2_out.stall <= '0';
slave1_o.err <= '0';
--slave2_out.err <= '0';
slave1_o.rty <= '0';
-- slave2_out.rty <= '0';
slave1_o.ack <= slave1_out.ack;
end struct;
hdl/boards/vfc/rtl/xwb_ram.vhd 0 → 100755
View file @ 4e89e511
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: xwb_ram.vhd
--______________________________________________________________________
-- Description: This block acts as WB Slave to test the vme64x interface
-- Block diagram:
-- ______________________
-- | |
-- | |
-- | __________ |
-- | | WB | |
-- | | LOGIC | |
-- W | | | |
-- B | | | |
-- | |__________| |
-- S | ______________ |
-- I | | | |
-- G | | | |
-- N | | RAM | |
-- A | | 64-bit port | |
-- L | | Byte | |
-- S | | Granularity | |
-- | | | |
-- | | | |
-- | | | |
-- | |______________| |
-- | |
-- | |
-- |______________________|
--
-- The RAM is a single port ram, 64 bit wide with byte granularity.
-- WB LOGIC: some processes add to generate the acknowledge and
-- the enable signals.
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity xwb_ram is
generic(
g_size : integer := c_SIZE;
g_init_file : string := "";
g_must_have_init_file : boolean := false;
g_slave1_interface_mode : t_wishbone_interface_mode;
g_slave1_granularity : t_wishbone_address_granularity
);
port(
clk_sys_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out
);
end xwb_ram;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture struct of xwb_ram is
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
signal s_wea : std_logic;
signal s_bwea : std_logic_vector(c_wishbone_data_width/8-1 downto 0);
signal slave1_out : t_wishbone_slave_out;
signal s_cyc : std_logic;
signal s_stb : std_logic;
signal s_rst : std_logic;
signal s_stall : std_logic;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
-- RAM memory
U_DPRAM : entity work.spram
generic map(
-- standard parameters
g_data_width => c_wishbone_data_width,
g_size => g_size,
g_with_byte_enable => true,
g_init_file => "",
g_addr_conflict_resolution => "read_first"
)
port map(
clk_i => clk_sys_i,
bwe_i => s_bwea,
a_i => slave1_i.adr(f_log2_size(g_size)-1 downto 0),
d_i => slave1_i.dat,
q_o => slave1_o.dat
);
-- WB Logic:
s_bwea <= slave1_i.sel when s_wea = '1' else f_zeros(c_wishbone_data_width/8);
s_wea <= slave1_i.we and slave1_i.cyc and slave1_i.stb and (not s_stall);
process(clk_sys_i)
begin
if(rising_edge(clk_sys_i)) then
if(slave1_out.ack = '1' and g_slave1_interface_mode = CLASSIC) then
slave1_out.ack <= '0';
else
slave1_out.ack <= slave1_i.cyc and slave1_i.stb and (not s_stall) ;
end if;
end if;
end process;
s_stall <= '0';
slave1_o.stall <= s_stall;
slave1_o.err <= '0'; --slave1_out.ack;
slave1_o.rty <= '0'; -- '0';
slave1_o.ack <= slave1_out.ack;
end struct;
--===========================================================================
-- Architecture end
--===========================================================================
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