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VME64x core
Commit 40557d7a authored by Tristan Gingold's avatar Tristan Gingold
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cr/csr: remove unimplemented ader to reduce number of registers.

parent ee2fd3cc
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Showing with 135 additions and 71 deletions
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ 40557d7a
...@@ -327,9 +327,19 @@ begin ...@@ -327,9 +327,19 @@ begin
-- Write -- Write
process (clk_i) process (clk_i)
variable v_addr : unsigned(18 downto 2); -- Write to ADER bytes, if implemented. Take advantage of VITAL-1-1 Rule
variable v_index : integer; -- 10.19
procedure set_ADER (Idx : natural range 0 to 7) is
variable v_byte : integer; variable v_byte : integer;
begin
if g_ADEM (Idx) /= x"0000_0000" then
v_byte := 3 - to_integer(s_addr(3 downto 2));
s_reg_ader(Idx)(8*v_byte+7 downto 8*v_byte) <= data_i;
end if;
end set_ADER;
variable csr_idx : unsigned(7 downto 4);
variable csr_boff : unsigned(3 downto 2);
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if rst_n_i = '0' then if rst_n_i = '0' then
...@@ -344,14 +354,16 @@ begin ...@@ -344,14 +354,16 @@ begin
s_reg_ader <= (others => x"00000000"); s_reg_ader <= (others => x"00000000");
else else
if we_i = '1' and s_csr_access = '1' then if we_i = '1' and s_csr_access = '1' then
case to_integer(s_addr) is csr_idx := s_addr(7 downto 4);
when c_BAR_REG => csr_boff := s_addr(3 downto 2);
case csr_idx is
when x"f" =>
case csr_boff is
when "11" => -- BAR
s_reg_bar <= data_i; s_reg_bar <= data_i;
when "10" => -- Bit Set
when c_BIT_SET_REG =>
s_reg_bit_reg <= s_reg_bit_reg or data_i; s_reg_bit_reg <= s_reg_bit_reg or data_i;
when "01" => -- Bit Clr
when c_BIT_CLR_REG =>
s_reg_bit_reg <= s_reg_bit_reg and not data_i; s_reg_bit_reg <= s_reg_bit_reg and not data_i;
-- VITAL-1-1 Rule 10.27 -- VITAL-1-1 Rule 10.27
-- 4) Ownership shall be released by writing any value with -- 4) Ownership shall be released by writing any value with
...@@ -362,8 +374,7 @@ begin ...@@ -362,8 +374,7 @@ begin
if data_i(c_CRAM_OWNER_BIT) = '1' then if data_i(c_CRAM_OWNER_BIT) = '1' then
s_reg_cram_owner <= x"00"; s_reg_cram_owner <= x"00";
end if; end if;
when "00" => -- CRAM_OWNER
when c_CRAM_OWNER_REG =>
-- VITAL-1-1 Rule 10.27 -- VITAL-1-1 Rule 10.27
-- 2) Writing to CRAM_OWNER register when it contains a non- -- 2) Writing to CRAM_OWNER register when it contains a non-
-- zero value shall not change the value of the -- zero value shall not change the value of the
...@@ -373,19 +384,36 @@ begin ...@@ -373,19 +384,36 @@ begin
s_reg_cram_owner <= data_i; s_reg_cram_owner <= data_i;
s_reg_bit_reg(c_CRAM_OWNER_BIT) <= '1'; s_reg_bit_reg(c_CRAM_OWNER_BIT) <= '1';
end if; end if;
when others =>
when c_USR_SET_REG => null;
end case;
when x"e" =>
case csr_boff is
when "11" => -- User Set
s_reg_usr_bit_reg <= s_reg_usr_bit_reg or data_i; s_reg_usr_bit_reg <= s_reg_usr_bit_reg or data_i;
when "10" => -- User Clr
when c_USR_CLR_REG =>
s_reg_usr_bit_reg <= s_reg_usr_bit_reg and not data_i; s_reg_usr_bit_reg <= s_reg_usr_bit_reg and not data_i;
when others =>
null;
end case;
when c_ADER_REG_BEG to c_ADER_REG_END => -- Decompose ADER so that unimplemented one can be removed.
v_addr := s_addr(18 downto 2) - to_unsigned(c_ADER_REG_BEG, 17); when x"d" => -- ADER 7
v_index := to_integer(v_addr(6 downto 4)); Set_ADER(7);
v_byte := 3-to_integer(v_addr(3 downto 2)); when x"c" => -- ADER 6
-- FIXME: force DFSR and XAM to 0 ? Set_ADER(6);
s_reg_ader(v_index)(8*v_byte+7 downto 8*v_byte) <= data_i; when x"b" => -- ADER 5
Set_ADER(5);
when x"a" => -- ADER 4
Set_ADER(4);
when x"9" => -- ADER 3
Set_ADER(3);
when x"8" => -- ADER 2
Set_ADER(2);
when x"7" => -- ADER 1
Set_ADER(1);
when x"6" => -- ADER 0
Set_ADER(0);
when others => when others =>
null; null;
...@@ -411,41 +439,77 @@ begin ...@@ -411,41 +439,77 @@ begin
-- Read -- Read
process (clk_i) process (clk_i)
procedure Get_ADER(Idx : natural range 0 to 7)
is
variable v_byte : integer;
begin
if g_ADEM(Idx) /= x"0000_0000" then
v_byte := 3 - to_integer(s_addr(3 downto 2));
s_csr_data <= s_reg_ader(Idx)(8*v_byte+7 downto 8*v_byte);
end if;
end Get_ADER;
variable csr_idx : unsigned(7 downto 4);
variable csr_boff : unsigned(3 downto 2);
variable v_addr : unsigned(18 downto 2); variable v_addr : unsigned(18 downto 2);
variable v_index : integer; variable v_index : integer;
variable v_byte : integer; variable v_byte : integer;
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if rst_n_i = '0' then if rst_n_i = '0' then
s_csr_data <= c_UNUSED; s_csr_data <= x"00";
else else
case to_integer(s_addr) is -- VITAL-1-1 Rule 10.14
when c_BAR_REG => -- All unimplemented locations in the Defined CSR Area shall read as
-- 0x00
s_csr_data <= x"00";
csr_idx := s_addr(7 downto 4);
csr_boff := s_addr(3 downto 2);
case csr_idx is
when x"f" =>
case csr_boff is
when "11" => -- BAR
s_csr_data <= s_reg_bar; s_csr_data <= s_reg_bar;
when "10" => -- Bit Set
when c_BIT_SET_REG =>
s_csr_data <= s_reg_bit_reg; s_csr_data <= s_reg_bit_reg;
when "01" => -- Bit Clr
when c_BIT_CLR_REG =>
s_csr_data <= s_reg_bit_reg; s_csr_data <= s_reg_bit_reg;
when "00" => -- CRAM_OWNER
when c_CRAM_OWNER_REG =>
s_csr_data <= s_reg_cram_owner; s_csr_data <= s_reg_cram_owner;
when others =>
when c_USR_SET_REG => null;
end case;
when x"e" =>
case csr_boff is
when "11" => -- User Set
s_csr_data <= s_reg_usr_bit_reg; s_csr_data <= s_reg_usr_bit_reg;
when "10" => -- User Clr
when c_USR_CLR_REG =>
s_csr_data <= s_reg_usr_bit_reg; s_csr_data <= s_reg_usr_bit_reg;
when others =>
null;
end case;
when c_ADER_REG_BEG to c_ADER_REG_END => -- Unroll to disable unused ADER. Not the best readable style.
v_addr := s_addr(18 downto 2) - to_unsigned(c_ADER_REG_BEG, 17); when x"d" =>
v_index := to_integer(v_addr(6 downto 4)); Get_ADER(7);
v_byte := 3-to_integer(v_addr(3 downto 2)); when x"c" =>
s_csr_data <= s_reg_ader(v_index)(8*v_byte+7 downto 8*v_byte); Get_ADER(6);
when x"b" =>
Get_ADER(5);
when x"a" =>
Get_ADER(4);
when x"9" =>
Get_ADER(3);
when x"8" =>
Get_ADER(2);
when x"7" =>
Get_ADER(1);
when x"6" =>
Get_ADER(0);
when others => when others =>
s_csr_data <= c_UNUSED; null;
end case; end case;
end if; end if;
end if; end if;
......
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