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VME64x core
Commit 24630ce1 authored by rstefanic's avatar rstefanic
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git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@31 665b4545-5c6b-4c24-801b-41150b02b44b
parent 5ab1bd72
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HDL/VME64e_ISE/VME64e_ISE.gise
View file @ 24630ce1
......@@ -22,6 +22,11 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="VME64e_ISE.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_COREGEN_PROJECT" xil_pn:name="../IP_cores/CRAM.cgp"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="../IP_cores/CRAM_readme.txt"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="../IP_cores/CR_readme.txt"/>
<file xil_pn:fileType="FILE_COREGEN_PROJECT" xil_pn:name="../IP_cores/FIFO.cgp"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="../IP_cores/FIFO_readme.txt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="VME64e_ISE.ntrc_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="VME64xCore_Top.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="VME64xCore_Top.cmd_log"/>
......@@ -47,12 +52,6 @@
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="ipcore_dir/CRAM_readme.txt"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="ipcore_dir/CR_readme.txt"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="ipcore_dir/FIFO_readme.txt"/>
<file xil_pn:fileType="FILE_COREGEN_PROJECT" xil_pn:name="ipcore_dir/coregen.cgp"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
<file xil_pn:fileType="FILE_RESPONSE" xil_pn:name="ipcore_dir/coregen.rsp"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
......@@ -63,25 +62,25 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1283416575" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="5084833147041544619" xil_pn:start_ts="1283416575">
<transform xil_pn:end_ts="1285746335" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="5084833147041544619" xil_pn:start_ts="1285746335">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1283417041" xil_pn:in_ck="-5981931411149976335" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5562680853294819280" xil_pn:start_ts="1283417041">
<transform xil_pn:end_ts="1285746336" xil_pn:in_ck="7401202389017945550" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5562680853294819280" xil_pn:start_ts="1285746335">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/CR.ngc"/>
<outfile xil_pn:name="ipcore_dir/CR.vhd"/>
<outfile xil_pn:name="ipcore_dir/CRAM.ngc"/>
<outfile xil_pn:name="ipcore_dir/CRAM.vhd"/>
<outfile xil_pn:name="ipcore_dir/FIFO.ngc"/>
<outfile xil_pn:name="ipcore_dir/FIFO.vhd"/>
<outfile xil_pn:name="../IP_cores/CR.ngc"/>
<outfile xil_pn:name="../IP_cores/CR.vhd"/>
<outfile xil_pn:name="../IP_cores/CRAM.ngc"/>
<outfile xil_pn:name="../IP_cores/CRAM.vhd"/>
<outfile xil_pn:name="../IP_cores/FIFO.ngc"/>
<outfile xil_pn:name="../IP_cores/FIFO.vhd"/>
</transform>
<transform xil_pn:name="TRAN_SubProjectAbstractToPreProxy">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1283416714" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3628963557787100221" xil_pn:start_ts="1283416714">
<transform xil_pn:end_ts="1285746336" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3628963557787100221" xil_pn:start_ts="1285746336">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
......@@ -89,16 +88,14 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1283416714" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="4316985326968841178" xil_pn:start_ts="1283416714">
<transform xil_pn:end_ts="1285746336" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="4316985326968841178" xil_pn:start_ts="1285746336">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1283417096" xil_pn:in_ck="-156755651022357249" xil_pn:name="TRANEXT_xstsynthesize_virtex5" xil_pn:prop_ck="-467913739352410528" xil_pn:start_ts="1283417041">
<transform xil_pn:end_ts="1285746397" xil_pn:in_ck="-4674645310522607386" xil_pn:name="TRANEXT_xstsynthesize_virtex5" xil_pn:prop_ck="-467913739352410528" xil_pn:start_ts="1285746336">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="VME64e_ISE.ntrc_log"/>
<outfile xil_pn:name="VME64xCore_Top.cmd_log"/>
<outfile xil_pn:name="VME64xCore_Top.lso"/>
......@@ -118,29 +115,28 @@
<transform xil_pn:end_ts="1283416798" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6878073351094540754" xil_pn:start_ts="1283416797">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform>
<transform xil_pn:end_ts="1283417102" xil_pn:in_ck="7368411555270321862" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="500526388826779459" xil_pn:start_ts="1283417096">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="VME64xCore_Top.bld"/>
<outfile xil_pn:name="VME64xCore_Top.cmd_log"/>
<outfile xil_pn:name="VME64xCore_Top.ngd"/>
<outfile xil_pn:name="VME64xCore_Top_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="xlnx_auto_0_xdb"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1283417120" xil_pn:in_ck="3990433084374946988" xil_pn:name="TRANEXT_map_virtex5" xil_pn:prop_ck="832886413622344519" xil_pn:start_ts="1283417102">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="VME64xCore_Top.pcf"/>
<outfile xil_pn:name="VME64xCore_Top_map.map"/>
<outfile xil_pn:name="VME64xCore_Top_map.mrp"/>
<outfile xil_pn:name="VME64xCore_Top_map.ncd"/>
<outfile xil_pn:name="VME64xCore_Top_map.ngm"/>
<outfile xil_pn:name="VME64xCore_Top_map.xrpt"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
</transforms>
......
HDL/VME64e_ISE/VME64e_ISE.xise
View file @ 24630ce1
......@@ -15,52 +15,49 @@
<version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="CR.ngc" xil_pn:type="FILE_NGC"/>
<file xil_pn:name="CRAM.ngc" xil_pn:type="FILE_NGC"/>
<file xil_pn:name="VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../VME64e_ActHDL_src/IRQ_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="VME_pack.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../VME64e_ActHDL_src/SharedComps.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="FIFO.ngc" xil_pn:type="FILE_NGC"/>
<file xil_pn:name="SharedComps.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../VME64e_ActHDL_src/VME_bus.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="IRQ_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../VME64e_ActHDL_src/VME_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="WB_bus.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../VME64e_ActHDL_src/VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="VME_bus.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../VME64e_ActHDL_src/WB_bus.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ipcore_dir/CRAM.xco" xil_pn:type="FILE_COREGEN">
<file xil_pn:name="../IP_cores/CR.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ipcore_dir/FIFO.xco" xil_pn:type="FILE_COREGEN">
<file xil_pn:name="../IP_cores/CRAM.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ipcore_dir/CR.xco" xil_pn:type="FILE_COREGEN">
<file xil_pn:name="../IP_cores/FIFO.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ipcore_dir/CRAM.xise" xil_pn:type="FILE_COREGENISE">
<file xil_pn:name="../IP_cores/CR.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ipcore_dir/FIFO.xise" xil_pn:type="FILE_COREGENISE">
<file xil_pn:name="../IP_cores/CRAM.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ipcore_dir/CR.xise" xil_pn:type="FILE_COREGENISE">
<file xil_pn:name="../IP_cores/FIFO.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
</files>
......@@ -136,6 +133,7 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Enhanced Design Summary" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -183,7 +181,7 @@
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|VME64xCore_Top|RTL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="VME64xCore_Top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../VME64e_ActHDL_src/VME64xCore_Top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/VME64xCore_Top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
......
HDL/VME64e_ISE/VME64xCore_Top.cmd_log
View file @ 24630ce1
......@@ -17,3 +17,4 @@ map -intstyle ise -p xc5vlx20t-ff323-2 -w -logic_opt off -ol high -t 1 -register
xst -intstyle ise -ifn "D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/VME64xCore_Top.xst" -ofn "D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/VME64xCore_Top.syr"
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc5vlx20t-ff323-2 VME64xCore_Top.ngc VME64xCore_Top.ngd
map -intstyle ise -p xc5vlx20t-ff323-2 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -cm area -ir off -pr off -lc off -power off -o VME64xCore_Top_map.ncd VME64xCore_Top.ngd VME64xCore_Top.pcf
xst -intstyle ise -ifn "D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/VME64xCore_Top.xst" -ofn "D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/VME64xCore_Top.syr"
HDL/VME64e_ISE/VME64xCore_Top.ngc
View file @ 24630ce1
This diff is collapsed.
HDL/VME64e_ISE/VME64xCore_Top.ngr
View file @ 24630ce1
This diff is collapsed.
HDL/VME64e_ISE/VME64xCore_Top.prj
View file @ 24630ce1
vhdl work "ipcore_dir/CRAM.vhd"
vhdl work "VME_pack.vhd"
vhdl work "SharedComps.vhd"
vhdl work "WB_bus.vhd"
vhdl work "VME_bus.vhd"
vhdl work "IRQ_controller.vhd"
vhdl work "ipcore_dir/FIFO.vhd"
vhdl work "ipcore_dir/CR.vhd"
vhdl work "VME64xCore_Top.vhd"
vhdl work "../IP_cores/CR.vhd"
vhdl work "../VME64e_ActHDL_src/VME_pack.vhd"
vhdl work "../VME64e_ActHDL_src/SharedComps.vhd"
vhdl work "../VME64e_ActHDL_src/WB_bus.vhd"
vhdl work "../VME64e_ActHDL_src/VME_bus.vhd"
vhdl work "../VME64e_ActHDL_src/IRQ_controller.vhd"
vhdl work "../IP_cores/FIFO.vhd"
vhdl work "../IP_cores/CRAM.vhd"
vhdl work "../VME64e_ActHDL_src/VME64xCore_Top.vhd"
HDL/VME64e_ISE/VME64xCore_Top.syr
View file @ 24630ce1
This diff is collapsed.
HDL/VME64e_ISE/VME64xCore_Top.xst
View file @ 24630ce1
......@@ -17,7 +17,7 @@ run
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-sd {"ipcore_dir" }
-sd {"../IP_cores" }
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
......
HDL/VME64e_ISE/VME64xCore_Top_vhdl.prj
View file @ 24630ce1
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ISE\ipcore_dir\CRAM.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ISE\VME_pack.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ISE\SharedComps.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ISE\WB_bus.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ISE\VME_bus.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ISE\IRQ_controller.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ISE\ipcore_dir\FIFO.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ISE\ipcore_dir\CR.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ISE\VME64xCore_Top.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\IP_cores\CR.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\VME_pack.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\SharedComps.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\WB_bus.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\VME_bus.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\IRQ_controller.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\IP_cores\FIFO.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\IP_cores\CRAM.vhd"
vhdl work "D:\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\VME64xCore_Top.vhd"
HDL/VME64e_ISE/VME64xCore_Top_xst.xrpt
View file @ 24630ce1
......@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Thu Sep 02 10:44:02 2010">
<application stringID="Xst" timeStamp="Wed Sep 29 09:45:39 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
......@@ -70,7 +70,7 @@
<item DEFAULT="NO" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
<item DEFAULT="ALLCLOCKNETS" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
<item DEFAULT="YES" label="-read_cores" stringID="XST_READCORES" value="YES"/>
<item DEFAULT="" label="-sd" stringID="XST_SD" value="{&quot;ipcore_dir&quot; }"/>
<item DEFAULT="" label="-sd" stringID="XST_SD" value="{&quot;../IP_cores&quot; }"/>
<item DEFAULT="NO" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
<item DEFAULT="NO" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
<item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/>
......@@ -123,19 +123,19 @@
<item dataType="int" stringID="XST_COUNTERS" value="3">
<item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="2"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="407">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="285"/>
<item dataType="int" stringID="XST_REGISTERS" value="417">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="293"/>
<item dataType="int" stringID="XST_18BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_2BIT_REGISTER" value="7"/>
<item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_32BIT_REGISTER" value="3"/>
<item dataType="int" stringID="XST_32BIT_REGISTER" value="4"/>
<item dataType="int" stringID="XST_4BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_6BIT_REGISTER" value="4"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="97"/>
</item>
<item dataType="int" stringID="XST_COMPARATORS" value="46"></item>
<item dataType="int" stringID="XST_TRISTATES" value="112">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="110"/>
<item dataType="int" stringID="XST_TRISTATES" value="105">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="102"/>
</item>
<item dataType="int" stringID="XST_XORS" value="4">
<item dataType="int" stringID="XST_1BIT_XOR2" value="3"/>
......@@ -151,8 +151,8 @@
<item dataType="int" stringID="XST_COUNTERS" value="3">
<item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="2"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="1550">
<item dataType="int" stringID="XST_FLIPFLOPS" value="1550"/>
<item dataType="int" stringID="XST_REGISTERS" value="1621">
<item dataType="int" stringID="XST_FLIPFLOPS" value="1621"/>
</item>
<item dataType="int" stringID="XST_COMPARATORS" value="45"></item>
<item dataType="int" stringID="XST_XORS" value="4">
......@@ -161,12 +161,12 @@
</item>
</section>
<section stringID="XST_FINAL_REGISTER_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="1330">
<item dataType="int" stringID="XST_FLIPFLOPS" value="1330"/>
<item dataType="int" stringID="XST_REGISTERS" value="1398">
<item dataType="int" stringID="XST_FLIPFLOPS" value="1398"/>
</item>
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="93">
<item dataType="int" stringID="XST_2BIT_SHIFT_REGISTER" value="6"/>
<item dataType="int" stringID="XST_3BIT_SHIFT_REGISTER" value="87"/>
<item dataType="int" stringID="XST_2BIT_SHIFT_REGISTER" value="5"/>
<item dataType="int" stringID="XST_3BIT_SHIFT_REGISTER" value="88"/>
</item>
</section>
<section stringID="XST_PARTITION_REPORT">
......@@ -186,30 +186,30 @@
<item stringID="XST_IOS" value="310"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="3508">
<item dataType="int" stringID="XST_BELS" value="3502">
<item dataType="int" stringID="XST_GND" value="5"/>
<item dataType="int" stringID="XST_INV" value="24"/>
<item dataType="int" stringID="XST_INV" value="25"/>
<item dataType="int" stringID="XST_LUT1" value="129"/>
<item dataType="int" stringID="XST_LUT2" value="239"/>
<item dataType="int" stringID="XST_LUT3" value="607"/>
<item dataType="int" stringID="XST_LUT4" value="350"/>
<item dataType="int" stringID="XST_LUT5" value="589"/>
<item dataType="int" stringID="XST_LUT6" value="694"/>
<item dataType="int" stringID="XST_LUT2" value="236"/>
<item dataType="int" stringID="XST_LUT3" value="592"/>
<item dataType="int" stringID="XST_LUT4" value="401"/>
<item dataType="int" stringID="XST_LUT5" value="562"/>
<item dataType="int" stringID="XST_LUT6" value="689"/>
<item dataType="int" stringID="XST_MUXCY" value="573"/>
<item dataType="int" stringID="XST_MUXF7" value="20"/>
<item dataType="int" stringID="XST_MUXF7" value="12"/>
<item dataType="int" stringID="XST_VCC" value="5"/>
<item dataType="int" stringID="XST_XORCY" value="273"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="1523">
<item dataType="int" stringID="XST_FD" value="31"/>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="1591">
<item dataType="int" stringID="XST_FD" value="62"/>
<item dataType="int" stringID="XST_FDCE" value="60"/>
<item dataType="int" stringID="XST_FDE" value="736"/>
<item dataType="int" stringID="XST_FDP" value="16"/>
<item dataType="int" stringID="XST_FDPE" value="8"/>
<item dataType="int" stringID="XST_FDR" value="61"/>
<item dataType="int" stringID="XST_FDR" value="66"/>
<item dataType="int" stringID="XST_FDRE" value="573"/>
<item dataType="int" stringID="XST_FDRS" value="21"/>
<item dataType="int" stringID="XST_FDS" value="6"/>
<item dataType="int" stringID="XST_FDS" value="38"/>
<item dataType="int" stringID="XST_FDSE" value="1"/>
</item>
<item dataType="int" stringID="XST_RAMS" value="4"></item>
......@@ -229,16 +229,16 @@
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="5vlx20tff323-2"/>
<item AVAILABLE="12480" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="1523"/>
<item AVAILABLE="12480" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="2725"/>
<item AVAILABLE="12480" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="2632"/>
<item AVAILABLE="12480" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="1591"/>
<item AVAILABLE="12480" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="2727"/>
<item AVAILABLE="12480" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="2634"/>
<item AVAILABLE="3360" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="93"/>
<item dataType="int" stringID="XST_NUMBER_USED_AS_SRL" value="93"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="3070"/>
<item AVAILABLE="3070" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="1547"/>
<item AVAILABLE="3070" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="345"/>
<item AVAILABLE="3070" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="1178"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="169"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="3092"/>
<item AVAILABLE="3092" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="1501"/>
<item AVAILABLE="3092" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="365"/>
<item AVAILABLE="3092" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="1226"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="182"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="310"/>
<item AVAILABLE="172" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="310"/>
<item AVAILABLE="26" dataType="int" label="Number of Block RAM/FIFO" stringID="XST_NUMBER_OF_BLOCK_RAMFIFO" value="4"/>
......@@ -250,8 +250,8 @@
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="144"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="36"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="174"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="37"/>
</section>
</application>
......
HDL/VME64e_ISE/_xmsgs/pn_parser.xmsgs
View file @ 24630ce1
......@@ -8,5 +8,8 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/SharedComps.vhd&quot; into library work</arg>
</msg>
</messages>
HDL/VME64e_ISE/_xmsgs/xst.xmsgs
View file @ 24630ce1
This diff is collapsed.
HDL/VME64e_ISE/iseconfig/VME64e_ISE.projectmgr
View file @ 24630ce1
<?xml version="1.0" encoding="utf-8"?>
<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
......@@ -10,13 +10,13 @@
<ClosedNode>/VME64xCore_Top - RTL/VME_bus_1 - VME_bus - RTL</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>VME64xCore_Top - RTL (D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/VME64xCore_Top.vhd)</SelectedItem>
<SelectedItem>VME64xCore_Top - RTL (D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/VME64xCore_Top.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000018f000000020000000000000000000000000000000064ffffffff0000008100000000000000020000018f0000000100000000000000000000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>VME64xCore_Top - RTL (D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/VME64xCore_Top.vhd)</CurrentItem>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000155000000020000000000000000000000000000000064ffffffff000000810000000000000002000001550000000100000000000000000000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>VME64xCore_Top - RTL (D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/VME64xCore_Top.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
......@@ -27,22 +27,24 @@
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Implement Design</SelectedItem>
<SelectedItem>Synthesize - XST</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000166000000010000000100000000000000000000000064ffffffff000000810000000000000001000001660000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Implement Design</CurrentItem>
<CurrentItem>Synthesize - XST</CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes/>
<SelectedItems/>
<SelectedItems>
<SelectedItem>SharedComps.vhd</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000018a000000040101000100000000000000000000000064ffffffff0000008100000000000000040000008600000001000000000000004400000001000000000000006600000001000000000000005a0000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000194000000040101000100000000000000000000000064ffffffff000000810000000000000004000000860000000100000000000000440000000100000000000000660000000100000000000000640000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>CR.ngc</CurrentItem>
<CurrentItem>SharedComps.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
......@@ -57,7 +59,11 @@
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>Synthesize - XST</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Add Existing Source</SelectedItem>
......
HDL/VME64e_ISE/webtalk_pn.xml
View file @ 24630ce1
......@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Thu Sep 02 10:44:02 2010">
<application name="pn" timeStamp="Wed Sep 29 09:45:36 2010">
<section name="Project Information" visible="false">
<property name="ProjectID" value="CC2EFF973BED43378257EA1E383BC629" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
......@@ -44,7 +44,6 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_DevSpeed" value="-2" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_COREGEN" value="3" type="source"/>
<property name="FILE_NGC" value="3" type="source"/>
<property name="FILE_VHDL" value="6" type="source"/>
</section>
</application>
......
HDL/VME64e_ISE/xst/work/hdllib.ref
View file @ 24630ce1
EN wb_bus NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/WB_bus.vhd sub00/vhpl15 1283417059
AR irq_controller rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/IRQ_controller.vhd sub00/vhpl18 1283417062
AR fifo fifo_a D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/ipcore_dir/FIFO.vhd sub00/vhpl22 1283417068
EN cr NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/ipcore_dir/CR.vhd sub00/vhpl25 1283417063
PH vme_pack NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/VME_pack.vhd sub00/vhpl12 1283417056
AR wb_bus rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/WB_bus.vhd sub00/vhpl16 1283417060
AR siginputsampleandrisingedgedetection rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/SharedComps.vhd sub00/vhpl07 1283417051
EN irq_controller NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/IRQ_controller.vhd sub00/vhpl17 1283417061
EN siginputsampleandedgedetection NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/SharedComps.vhd sub00/vhpl08 1283417052
AR cr cr_a D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/ipcore_dir/CR.vhd sub00/vhpl26 1283417064
EN siginputsampleandrisingedgedetection NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/SharedComps.vhd sub00/vhpl06 1283417050
AR reginputsample rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/SharedComps.vhd sub00/vhpl11 1283417055
AR vme64xcore_top rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/VME64xCore_Top.vhd sub00/vhpl24 1283417070
EN siginputsampleandfallingedgedetection NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/SharedComps.vhd sub00/vhpl04 1283417048
EN risedgedetection NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/SharedComps.vhd sub00/vhpl02 1283417046
AR siginputsampleandfallingedgedetection rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/SharedComps.vhd sub00/vhpl05 1283417049
EN siginputsample NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/SharedComps.vhd sub00/vhpl00 1283417044
EN reginputsample NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/SharedComps.vhd sub00/vhpl10 1283417054
AR cram cram_a D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/ipcore_dir/CRAM.vhd sub00/vhpl20 1283417066
EN fifo NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/ipcore_dir/FIFO.vhd sub00/vhpl21 1283417067
EN vme_bus NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/VME_bus.vhd sub00/vhpl13 1283417057
AR siginputsample rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/SharedComps.vhd sub00/vhpl01 1283417045
AR siginputsampleandedgedetection rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/SharedComps.vhd sub00/vhpl09 1283417053
EN cram NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/ipcore_dir/CRAM.vhd sub00/vhpl19 1283417065
EN vme64xcore_top NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/VME64xCore_Top.vhd sub00/vhpl23 1283417069
AR risedgedetection rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/SharedComps.vhd sub00/vhpl03 1283417047
AR vme_bus rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ISE/VME_bus.vhd sub00/vhpl14 1283417058
EN wb_bus NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/WB_bus.vhd sub00/vhpl15 1285746357
AR irq_controller rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/IRQ_controller.vhd sub00/vhpl18 1285746360
AR fifo fifo_a D:/SVN/FAIR-VME64ext/trunk/HDL/IP_cores/FIFO.vhd sub00/vhpl22 1285746366
EN cr NULL D:/SVN/FAIR-VME64ext/trunk/HDL/IP_cores/CR.vhd sub00/vhpl25 1285746361
PH vme_pack NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/VME_pack.vhd sub00/vhpl12 1285746354
AR wb_bus rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/WB_bus.vhd sub00/vhpl16 1285746358
AR siginputsampleandrisingedgedetection rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/SharedComps.vhd sub00/vhpl07 1285746349
EN irq_controller NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/IRQ_controller.vhd sub00/vhpl17 1285746359
EN siginputsampleandedgedetection NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/SharedComps.vhd sub00/vhpl08 1285746350
AR cr cr_a D:/SVN/FAIR-VME64ext/trunk/HDL/IP_cores/CR.vhd sub00/vhpl26 1285746362
EN siginputsampleandrisingedgedetection NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/SharedComps.vhd sub00/vhpl06 1285746348
AR reginputsample rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/SharedComps.vhd sub00/vhpl11 1285746353
AR vme64xcore_top rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/VME64xCore_Top.vhd sub00/vhpl24 1285746368
EN siginputsampleandfallingedgedetection NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/SharedComps.vhd sub00/vhpl04 1285746346
EN risedgedetection NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/SharedComps.vhd sub00/vhpl02 1285746344
AR siginputsampleandfallingedgedetection rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/SharedComps.vhd sub00/vhpl05 1285746347
EN siginputsample NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/SharedComps.vhd sub00/vhpl00 1285746342
EN reginputsample NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/SharedComps.vhd sub00/vhpl10 1285746352
AR cram cram_a D:/SVN/FAIR-VME64ext/trunk/HDL/IP_cores/CRAM.vhd sub00/vhpl20 1285746364
EN fifo NULL D:/SVN/FAIR-VME64ext/trunk/HDL/IP_cores/FIFO.vhd sub00/vhpl21 1285746365
EN vme_bus NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/VME_bus.vhd sub00/vhpl13 1285746355
AR siginputsample rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/SharedComps.vhd sub00/vhpl01 1285746343
AR siginputsampleandedgedetection rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/SharedComps.vhd sub00/vhpl09 1285746351
EN cram NULL D:/SVN/FAIR-VME64ext/trunk/HDL/IP_cores/CRAM.vhd sub00/vhpl19 1285746363
EN vme64xcore_top NULL D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/VME64xCore_Top.vhd sub00/vhpl23 1285746367
AR risedgedetection rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/SharedComps.vhd sub00/vhpl03 1285746345
AR vme_bus rtl D:/SVN/FAIR-VME64ext/trunk/HDL/VME64e_ActHDL_src/VME_bus.vhd sub00/vhpl14 1285746356
HDL/VME64e_ISE/xst/work/hdpdeps.ref
View file @ 24630ce1
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