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VME64x core
Commit 16799dda authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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sim: refactored common BFM stuff into a separat package, added a manifest for hdlmake too.

parent d1f817e8
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Manifest.py
View file @ 16799dda
modules = {"local" : ["hdl/rtl"]}
modules = {"local" : ["hdl/rtl" ]}
hdl/sim/vme64x_bfm/Manifest.py 0 → 100644
View file @ 16799dda
files = ["vme64x_bfm_pkg.sv",
"svec_vme_buffers.sv",
"components/sn74vmeh22501.v" ];
hdl/sim/vme64x_bfm/svec_vme_buffers.svh → hdl/sim/vme64x_bfm/svec_vme_buffers.sv
View file @ 16799dda
`include "components/sn74vmeh22501.v"
`include "vme64x_bfm.svh"
`timescale 1ns/1ps
module bidir_buf(
a,
......
hdl/sim/vme64x_bfm/vme64x_bfm_defs.svh 0 → 100644
View file @ 16799dda
`ifndef __VME64X_BFM_DEFS_SVH
`define __VME64X_BFM_DEFS_SVH 1
`define DECLARE_VME_BUFFERS(iface) \
wire VME_AS_n;\
wire VME_RST_n;\
wire VME_WRITE_n;\
wire [5:0] VME_AM;\
wire [1:0] VME_DS_n;\
wire [5:0] VME_GA; \
wire VME_BERR;\
wire VME_DTACK_n;\
wire VME_RETRY_n;\
wire VME_RETRY_OE;\
wire VME_LWORD_n;\
wire [31:1]VME_ADDR;\
wire [31:0]VME_DATA;\
wire VME_BBSY_n;\
wire [6:0]VME_IRQ_n;\
wire VME_IACKIN_n,VME_IACK_n;\
wire VME_IACKOUT_n;\
wire VME_DTACK_OE;\
wire VME_DATA_DIR;\
wire VME_DATA_OE_N;\
wire VME_ADDR_DIR;\
wire VME_ADDR_OE_N;\
svec_vme_buffers U_VME_Bufs ( \
.VME_AS_n_o(VME_AS_n),\
.VME_RST_n_o(VME_RST_n),\
.VME_WRITE_n_o(VME_WRITE_n),\
.VME_AM_o(VME_AM),\
.VME_GA_o(VME_GA),\
.VME_DS_n_o(VME_DS_n),\
.VME_BERR_i(VME_BERR),\
.VME_DTACK_n_i(VME_DTACK_n),\
.VME_RETRY_n_i(VME_RETRY_n),\
.VME_RETRY_OE_i(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_BBSY_n_o(VME_BBSY_n),\
.VME_IRQ_n_i(VME_IRQ_n),\
.VME_IACK_n_o(VME_IACK_n),\
.VME_IACKIN_n_o(VME_IACKIN_n),\
.VME_IACKOUT_n_i(VME_IACKOUT_n),\
.VME_DTACK_OE_i(VME_DTACK_OE),\
.VME_DATA_DIR_i(VME_DATA_DIR),\
.VME_DATA_OE_N_i(VME_DATA_OE_N),\
.VME_ADDR_DIR_i(VME_ADDR_DIR),\
.VME_ADDR_OE_N_i(VME_ADDR_OE_N),\
.slave(iface)\
);
function automatic bit[5:0] _gen_ga(int slot);
bit[4:0] slot_id = slot;
return {^slot_id, ~slot_id};
endfunction // _gen_ga
`define WIRE_VME_PINS(slot_id) \
.VME_AS_n_i(VME_AS_n),\
.VME_RST_n_i(VME_RST_n),\
.VME_WRITE_n_i(VME_WRITE_n),\
.VME_AM_i(VME_AM),\
.VME_DS_n_i(VME_DS_n),\
.VME_GA_i(_gen_ga(slot_id)),\
.VME_BERR_o(VME_BERR),\
.VME_DTACK_n_o(VME_DTACK_n),\
.VME_RETRY_n_o(VME_RETRY_n),\
.VME_RETRY_OE_o(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_BBSY_n_i(VME_BBSY_n),\
.VME_IRQ_n_o(VME_IRQ_n),\
.VME_IACK_n_i(VME_IACK_n),\
.VME_IACKIN_n_i(VME_IACKIN_n),\
.VME_IACKOUT_n_o(VME_IACKOUT_n),\
.VME_DTACK_OE_o(VME_DTACK_OE),\
.VME_DATA_DIR_o(VME_DATA_DIR),\
.VME_DATA_OE_N_o(VME_DATA_OE_N),\
.VME_ADDR_DIR_o(VME_ADDR_DIR),\
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
`endif
hdl/sim/vme64x_bfm/vme64x_bfm.svh → hdl/sim/vme64x_bfm/vme64x_bfm_pkg.sv
View file @ 16799dda
`ifndef __VME64X_BFM_SVH
`define __VME64X_BFM_SVH 1
`timescale 1ns/1ps
`include "simdrv_defs.svh"
`define assert_wait(name, condition, timeout) \
begin\
time t=$time;\
......@@ -168,6 +163,11 @@ interface IVME64X ( input sys_rst_n_i );
endinterface // IVME64x
package vme64x_bfm_pkg;
`include "gencores_sim_defs.svh"
import gencores_sim_pkg::CBusAccessor;
const uint64_t CSR_BAR = 'h7FFFF;
const uint64_t CSR_BIT_SET_REG = 'h7FFFB;
......@@ -299,7 +299,7 @@ class CBusAccessor_VME64x extends CBusAccessor;
/* Simple generic VME read/write: single, BLT and CSR xfers */
protected task rw_generic(bit write, uint64_t _addr, ref uint64_t _data[], input vme_addr_size_t asize, input vme_xfer_type_t xtype, vme_data_type_t dtype);
protected task rw_generic(bit write, uint64_t _addr, ref u64_vector_t _data, input vme_addr_size_t asize, input vme_xfer_type_t xtype, vme_data_type_t dtype);
bit[3:0] dt;
int i;
......@@ -413,7 +413,7 @@ class CBusAccessor_VME64x extends CBusAccessor;
endtask // set_default_modifiers
task writem(uint64_t addr[], uint64_t data[], input int size = m_default_modifiers, ref int result);
task writem( input u64_vector_t addr, u64_vector_t data, input int size = m_default_modifiers, ref int result);
int i;
vme_addr_size_t asize;
vme_data_type_t dtype;
......@@ -423,9 +423,7 @@ class CBusAccessor_VME64x extends CBusAccessor;
if(xtype == SINGLE || xtype == CR_CSR)
for(i=0;i<addr.size();i++)
begin
uint64_t tmp[];
tmp = new[1];
tmp[0] = data[i];
automatic u64_vector_t tmp = '{ data[i] };
rw_generic(1, addr[i], tmp, asize, xtype, dtype);
end
else if (xtype == BLT)
......@@ -433,7 +431,7 @@ class CBusAccessor_VME64x extends CBusAccessor;
endtask // writem
task readm(uint64_t addr[], ref uint64_t data[], input int size = m_default_modifiers, ref int result);
task readm( input u64_vector_t addr, ref u64_vector_t data, input int size = m_default_modifiers, ref int result);
int i;
vme_addr_size_t asize;
......@@ -447,11 +445,7 @@ class CBusAccessor_VME64x extends CBusAccessor;
begin
for(i=0;i<addr.size();i++)
begin
uint64_t tmp[] = new[1];
tmp[0]=0;
automatic u64_vector_t tmp = '{ 0 };
rw_generic(0, addr[i], tmp, asize, xtype, dtype);
data[i] = tmp[0];
end
......@@ -474,13 +468,7 @@ class CBusAccessor_VME64x extends CBusAccessor;
task read(uint64_t addr, ref uint64_t data, input int size = m_default_modifiers, ref int result = _null);
int res;
uint64_t aa[1], da[];
//$display("AM=%x", size);
da= new[1];
aa[0] = addr;
u64_vector_t aa = '{ addr }, da = '{ 0 };
readm(aa, da, size, res);
data = da[0];
endtask
......@@ -518,5 +506,5 @@ class CBusAccessor_VME64x extends CBusAccessor;
end
endtask // handle_irqs
endclass // CBusAccessor_VME64x
`endif // `ifndef __VME64X_BFM_SVH
endpackage
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