Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
V
VME64x core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
VME64x core
Commits
15926779
Commit
15926779
authored
Nov 13, 2017
by
Maciej Lipinski
Committed by
Tristan Gingold
Nov 13, 2017
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
[desc] small corrections to VME_IRQ_Controller.vhd file
parent
f9505f15
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
7 additions
and
7 deletions
+7
-7
VME_IRQ_Controller.vhd
hdl/rtl/VME_IRQ_Controller.vhd
+7
-7
No files found.
hdl/rtl/VME_IRQ_Controller.vhd
View file @
15926779
...
...
@@ -19,7 +19,7 @@
-- --> request of a service.
-- The Interrupt priority is specificated by the Master writing the
-- INT_Level register in the CR/CSR space
-- 3) The Interrupter Controller wait for the falling edge on the VME_IACKIN
-- 3) The Interrupter Controller wait
s
for the falling edge on the VME_IACKIN
-- line.
-- 4) When detects VME_IACKIN_n_i = '0' and the Interrupt Handler initiates
-- the Interrupt cycle by asserting AS,the Interrupt Controller check if it
...
...
@@ -30,7 +30,7 @@
-- during the interrupt acknowledge cycle should be equal or greater than
-- the size the it can respond with, and it shall receive a falling edge on
-- its IACKIN*.
-- 5) If it is the responding interrupter should send the source/ID on the
-- 5) If it is the responding interrupter
, it
should send the source/ID on the
-- VME_DATA lines (in our case the source/ID is the INT_Vector that the
-- Master can write in the corresponding register in the CR/CSR space) and
-- it terminates the interrupt cycle with an acknowledge before releasing
...
...
@@ -39,7 +39,7 @@
--
-- All the output signals are registered
--
-- To implement the
5 phases before mentioned the follow
FSM has been
-- To implement the
above-mentioned 5 phases, the following
FSM has been
-- implemented:
-- __________
-- |--| IACKOUT2 |<-|
...
...
@@ -91,9 +91,9 @@
-- _______________________________________________________/\_________
--
-- To respect the time constraint indicated with the number 35 fig. 55 pag. 183
-- in the "VMEbus Specification" ANSI/IEEE STD1014-1987, is necessary to
-- generate the VME_AS1_n_i signal which is the AS signal
not sampled, and
-- assign this signal to the s_IACKOUT signal when the fsm is in the IACKOUTx
-- in the "VMEbus Specification" ANSI/IEEE STD1014-1987, i
t i
s necessary to
-- generate the VME_AS1_n_i signal which is the AS signal
that is not sampled,
-- a
nd a
ssign this signal to the s_IACKOUT signal when the fsm is in the IACKOUTx
-- state.
--
-- The LWORD* input is not used now, since this is a D08(O) Interrupter (see
...
...
@@ -153,7 +153,7 @@ architecture Behavioral of VME_IRQ_Controller is
begin
irq_pending_o
<=
s_irq_pending
;
-- Interrupts are automatically masked for g_RETRY_TIMEOUT (i
e
1 ms) once
-- Interrupts are automatically masked for g_RETRY_TIMEOUT (i
.e.
1 ms) once
-- they are acknowledge by the interrupt handler until they are deasserted
-- by the interrupter.
p_retry_fsm
:
process
(
clk_i
)
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment