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VME64x core
Commit 14081a92 authored by rstefanic's avatar rstefanic
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git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@22 665b4545-5c6b-4c24-801b-41150b02b44b
parent b36b4ab9
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HDL/VME64e_ActHDL/VME64xCore.wsw
View file @ 14081a92
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\references\VME64_slave_verilog\ga_decoder.v|]
TemplateId=2
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\VME64xCore\src\compile.do|]
TemplateId=6
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\VME64e_ActHDL_src\VME_bus.vhd|]
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\VME64e_ActHDL_src\WB_bus.vhd|]
TemplateId=0
ActiveDocument=1
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\VME64xCore\src\VME_unaligned_test.tcl|]
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\VME64e_ActHDL_src\IRQ_controller.vhd|]
TemplateId=0
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\VME64e_ActHDL_src\VME_bus.vhd|]
TemplateId=0
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\VME64e_ActHDL_src\VME64xCore_Top.vhd|]
TemplateId=0
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\VME64xCore\src\VME_top_test.tcl|]
TemplateId=7
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\VME64xCore\src\compile.do|]
TemplateId=6
[OPENDOC|Aldec.WaveFormASDB.7|.\VME64xCore\src\wave.asdb|]
TemplateId=0
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\VME64e_ActHDL_src\VME_pack.vhd|]
TemplateId=0
HDL/VME64e_ActHDL/VME64xCore/VME64xCore.LIB
View file @ 14081a92
timestamp=1273754497258
timestamp=1274258923148
[~A]
ModifyID=1
......
HDL/VME64e_ActHDL/VME64xCore/VME64xCore.adf
View file @ 14081a92
......@@ -36,7 +36,7 @@ Celoxica=0
UseCeloxica=0
PHYSSYNTH_STATUS=none
RUN_MODE_SYNTH=0
SYNTH_STATUS=warnings
SYNTH_STATUS=none
IMPL_STATUS=none
PCBINTERFACE_STATUS=NONE
C_SERVER_SIM=
......@@ -168,7 +168,7 @@ MOVE_LAST_FF_STAGE=1
JOB_DESCRIPTION=JobDesc1
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log*.*:implement*.*
LAST_RUN=1273740002
LAST_RUN=1274270640
OUTPUT_NETLIST=d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL\VME64xCore\synthesis\vme64xcore_top.ngc
OUTPUT_SIMUL_NETLIST=synthesis\vme64xcore_top.vhd
Show_SliceUtilizationRatioDelta=100
......@@ -211,6 +211,7 @@ post-synthesis=1
/VME_CRCSR_test.tcl=-1
/VME_init_test.tcl=-1
/VME_top_test.tcl=-1
/WB_pipelined_test.tcl=-1
post-synthesis/..\..\synthesis\vme64xcore_top.vhd=-1
[Files.Data]
......@@ -228,5 +229,6 @@ post-synthesis/..\..\synthesis\vme64xcore_top.vhd=-1
.\src\VME_CRCSR_test.tcl=Tcl Script
.\src\VME_init_test.tcl=Tcl Script
.\src\VME_top_test.tcl=Tcl Script
.\src\WB_pipelined_test.tcl=Tcl Script
.\synthesis\vme64xcore_top.vhd=VHDL Source Code
HDL/VME64e_ActHDL/VME64xCore/VME64xCore.wsp
View file @ 14081a92
......@@ -227,55 +227,51 @@ WindowWorkspaceInfo=2C0000000000000003000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB00
[Gui config]
RunFor=100 ns
[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\WB_bus.vhd|]
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WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB0000005E0000009006000003030000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000012
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB83FFFF3483FFFF9089FFFFD985FFFF000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C8000000000000000000000000000000000000000900000001000000C1
[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\IRQ_controller.vhd|]
CurrentLine=29
CurrentColumn=5
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WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB0000005E0000009006000003030000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000012
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB83FFFF3483FFFF9089FFFFD985FFFF000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C8000000000000000000000000000000000000000900000001000000C1
[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\VME_bus.vhd|]
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[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\VME64xCore_Top.vhd|]
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WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB83FFFF3483FFFF9089FFFFD985FFFF000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C8000000000000000000000000000000000000000900000001000000C1
[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL\VME64xCore\src\VME_top_test.tcl|]
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CurrentColumn=6
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BookmarksLength=3
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[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\VME_pack.vhd|]
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[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL\VME64xCore\src\compile.do|]
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[CACHEDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\VME_pack.vhd|]
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[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\VME_pack.vhd|]
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[CACHESIMPLE|Aldec.SymbolsCommands.7]
vme64xcore=1
Built-in symbols=0
VIRTEX5=0
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB83FFFF3483FFFF9089FFFFD985FFFF000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C8000000000000000000000000000000000000000900000001000000C1
HDL/VME64e_ActHDL/VME64xCore/compile.cfg
View file @ 14081a92
......@@ -13,8 +13,8 @@ File Time Hi=30071924
Enabled=1
State=Compiled
[file:.\..\..\VME64e_ActHDL_src\VME_bus.vhd]
File Time Lo=284683160
File Time Hi=30077558
File Time Lo=1177296936
File Time Hi=30078767
Enabled=1
State=Compiled
[file:.\src\VME_D08_test.tcl]
......@@ -43,8 +43,8 @@ File Time Hi=30066503
Enabled=1
State=Modified
[file:.\..\..\VME64e_ActHDL_src\VME_pack.vhd]
File Time Lo=-2074493802
File Time Hi=30077157
File Time Lo=1137797161
File Time Hi=30078761
Enabled=1
State=Compiled
[file:.\src\VME_init_test.tcl]
......@@ -54,27 +54,27 @@ Enabled=1
State=Modified
[file:.\src\VME_top_test.tcl]
State=Modified
File Time Lo=1956157623
File Time Hi=30071958
File Time Lo=277660624
File Time Hi=30078391
Enabled=1
[file:.\..\..\VME64e_ActHDL_src\VME64xCore_Top.vhd]
File Time Lo=-1069391231
File Time Hi=30077585
File Time Lo=-1419907683
File Time Hi=30078761
Enabled=1
State=Modified
State=Compiled
[file:.\..\..\VME64e_ActHDL_src\WB_bus.vhd]
File Time Lo=-1767308601
File Time Hi=30077593
File Time Lo=-1313887796
File Time Hi=30078767
Enabled=1
State=Modified
State=Compiled
[file:.\..\..\VME64e_ActHDL_src\IRQ_controller.vhd]
File Time Lo=-828597230
File Time Hi=30077001
File Time Lo=868158066
File Time Hi=30078760
Enabled=1
State=Compiled
[file:.\synthesis\vme64xcore_top.vhd]
File Time Lo=2020889689
File Time Hi=30071704
File Time Lo=-2137840593
File Time Hi=30078795
Enabled=1
State=Modified
LIB=vme64xcore_post_synthesis
......@@ -82,3 +82,8 @@ SIM.POST.INCLUDED=1
SIM.FUNC.INCLUDED=0
SIM.POST.AUTO=1
SIM.POST.INDEX=0
[file:.\src\WB_pipelined_test.tcl]
File Time Lo=-1320062172
File Time Hi=30078367
Enabled=1
State=Modified
HDL/VME64e_ActHDL/VME64xCore/elaboration.log
View file @ 14081a92
elbread.dll ver. 1.0.5.375 Tue May 11 10:47:00 2010
elbread.dll ver. 1.0.5.375 Mon May 17 13:49:57 2010
---------------------------------------------------------------------
......
HDL/VME64e_ActHDL_src/IRQ_controller.vhd
View file @ 14081a92
......@@ -74,6 +74,8 @@ signal VME_DS_n_oversampled : STD_LOGIC_VECTOR(1 downto 0);
signal s_reset: std_logic;
signal s_VME_IACKOUT: std_logic;
signal s_irqDTACK: std_logic; -- acknowledge of IACK cycle
signal s_applyIRQmask: std_logic; -- clears acknowlegded interrupt
signal s_IDtoData: std_logic; -- puts IRQ Status/ID register on data bus
......@@ -82,21 +84,28 @@ signal s_wbIRQrisingEdge: std_logic; -- rising edge detectio
signal s_IRQenabled: std_logic; -- indicates that interrupts are enabled (IRQlevelReg has a valid level value)
signal s_IRQreg: std_logic; -- registers pending interrupt
type t_IRQstates is (IDLE, WAIT_FOR_DS, CHECK_MATCH, APPLY_MASK_AND_DATA, PROPAGATE_IACK, APPLY_DTACK);
type t_IRQstates is ( IDLE,
WAIT_FOR_DS,
CHECK_MATCH,
APPLY_MASK_AND_DATA,
PROPAGATE_IACK,
APPLY_DTACK
);
signal s_IRQstate: t_IRQstates;
begin
s_reset <= reset_i;
irqDTACK_o <= s_irqDTACK;
irqDTACK_o <= '0' when s_irqDTACK='0' else 'Z';
VME_IACKOUT_n_o <= '0' when s_VME_IACKOUT='0' else 'Z';
p_IRQcontrolFSM: process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset='1' then
VME_IACKOUT_n_o <= 'Z';
s_irqDTACK <= 'Z';
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
......@@ -105,8 +114,8 @@ begin
case s_IRQstate is
when IDLE =>
VME_IACKOUT_n_o <= 'Z';
s_irqDTACK <= 'Z';
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
......@@ -117,8 +126,8 @@ begin
end if;
when WAIT_FOR_DS =>
VME_IACKOUT_n_o <= 'Z';
s_irqDTACK <= 'Z';
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
......@@ -129,11 +138,11 @@ begin
end if;
when CHECK_MATCH =>
VME_IACKOUT_n_o <= 'Z';
s_irqDTACK <= 'Z';
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o<= '0';
IACKinProgress_o <= '0';
if s_IACKmatch='1' then
s_IRQstate <= APPLY_MASK_AND_DATA;
else
......@@ -141,15 +150,15 @@ begin
end if;
when APPLY_MASK_AND_DATA =>
VME_IACKOUT_n_o <= 'Z';
s_irqDTACK <= 'Z';
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '1';
s_IDtoData <= '1';
IACKinProgress_o <= '1';
s_IRQstate <= APPLY_DTACK;
when APPLY_DTACK =>
VME_IACKOUT_n_o <= 'Z';
s_VME_IACKOUT <= '1';
s_irqDTACK <= '0';
s_applyIRQmask <= '0';
s_IDtoData <= '1';
......@@ -161,8 +170,8 @@ begin
end if;
when PROPAGATE_IACK =>
VME_IACKOUT_n_o <= VME_IACKIN_n_oversampled;
s_irqDTACK <= 'Z';
s_VME_IACKOUT <= VME_IACKIN_n_oversampled;
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
......@@ -173,8 +182,8 @@ begin
end if;
when OTHERS =>
VME_IACKOUT_n_o <= 'Z';
s_irqDTACK <= 'Z';
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
......@@ -203,9 +212,7 @@ begin
elsif s_applyIRQmask='1' then
s_IRQreg <= '0';
else
if s_wbIRQrisingEdge='1' and s_IRQenabled='1' then
s_IRQreg <= '1';
end if;
s_IRQreg <= s_wbIRQrisingEdge and s_IRQenabled;
end if;
end if;
end process;
......
HDL/VME64e_ActHDL_src/VME64xCore_Top.vhd
View file @ 14081a92
......@@ -172,7 +172,6 @@ component WB_bus is
ACK_i: in std_logic;
WE_o: out std_logic;
STALL_i: in std_logic;
IRQ_i: in std_logic;
memReq_i: in std_logic;
memAck_o: out std_logic;
......@@ -182,7 +181,6 @@ component WB_bus is
sel_i: in std_logic_vector(7 downto 0);
RW_i: in std_logic;
lock_i: in std_logic;
IRQ_o: out std_logic;
err_o: out std_logic;
rty_o: out std_logic;
cyc_i: in std_logic;
......@@ -192,7 +190,8 @@ component WB_bus is
FIFOrden_o: out std_logic;
FIFOwren_o: out std_logic;
FIFOdata_i: in std_logic_vector(63 downto 0);
FIFOdata_o: out std_logic_vector(63 downto 0);
FIFOdata_o: out std_logic_vector(63 downto 0);
FIFOreset_o: out std_logic;
writeFIFOempty_i: in std_logic;
TWOeInProgress_i: in std_logic;
WBbusy_o: out std_logic
......@@ -283,6 +282,8 @@ signal s_FIFOwriteEmpty: std_logic;
signal s_FIFOfull: std_logic;
signal s_FIFOwriteRden: std_logic;
signal s_FIFOreadRden: std_logic;
signal s_wbFIFOreset: std_logic;
signal s_FIFOreset: std_logic;
signal s_TWOeInProgress: std_logic;
signal s_WBbusy: std_logic;
signal s_beatCount: std_logic_vector(7 downto 0);
......@@ -297,7 +298,10 @@ begin
--CRAMdata_o <= s_CRAMdataIn;
--CRAMwea_o <= s_CRAMwea;
--CRaddr_o <= s_CRaddr;
--s_CRdata <= CRdata_i;
--s_CRdata <= CRdata_i;
s_FIFOreset <= s_wbFIFOreset or s_reset;
VME_bus_1 : VME_bus
port map(
......@@ -378,7 +382,6 @@ WB_bus_1: WB_bus
ACK_i => ACK_i,
WE_o => WE_o,
STALL_i => STALL_i,
IRQ_i => IRQ_i,
memReq_i => s_memReq,
memAck_o => s_memAckWB,
......@@ -388,7 +391,6 @@ WB_bus_1: WB_bus
sel_i => s_wbSel,
RW_i => s_RW,
lock_i => s_lock,
IRQ_o => s_IRQ,
err_o => s_err,
rty_o => s_rty,
cyc_i => s_cyc,
......@@ -398,6 +400,7 @@ WB_bus_1: WB_bus
FIFOwren_o => s_FIFOreadWren,
FIFOdata_i => s_FIFOwriteDout,
FIFOdata_o => s_FIFOreadDin,
FIFOreset_o => s_wbFIFOreset,
writeFIFOempty_i => s_FIFOwriteEmpty,
TWOeInProgress_i => s_TWOeInProgress,
WBbusy_o => s_WBbusy
......@@ -444,7 +447,7 @@ FIFO_write: FIFO
clk => clk_i,
din => s_FIFOwriteDin,
rd_en => s_FIFOwriteRden,
rst => s_reset,
rst => s_FIFOreset,
wr_en => s_FIFOwriteWren,
dout => s_FIFOwriteDout,
empty => s_FIFOwriteEmpty,
......@@ -456,7 +459,7 @@ FIFO_read: FIFO
clk => clk_i,
din => s_FIFOreadDin,
rd_en => s_FIFOreadRden,
rst => s_reset,
rst => s_FIFOreset,
wr_en => s_FIFOreadWren,
dout => s_FIFOreadDout,
empty => s_FIFOreadEmpty,
......
HDL/VME64e_ActHDL_src/VME_bus.vhd
View file @ 14081a92
......@@ -316,7 +316,8 @@ signal s_berr_2: std_logic; --
-- Access decode signals
signal s_confAccess: std_logic; -- Asserted when CR or CSR is addressed
signal s_cardSel: std_logic; -- Asserted when internal memory space is addressed
signal s_cardSel: std_logic; -- Asserted when internal memory space is addressed
signal s_lockSel: std_logic; -- Asserted when function losk is correctly addressed
signal s_memAckCaseCondition: std_logic_vector(1 downto 0); -- Used in p_memAck for case condition
signal s_XAM: std_logic_vector(7 downto 0); -- Stores received XAM
......@@ -394,9 +395,9 @@ begin
s_reset <= (not VME_RST_n_oversampled) or s_CSRarray(BIT_SET_CLR_REG)(7); -- hardware reset and software reset
reset_o <= s_reset;
VME_DTACK_OE_o <= s_dtackOE;
VME_DATA_DIR_o <= s_dataDir;
VME_DATA_OE_o <= s_dataOE;
VME_DTACK_OE_o <= '1' when IACKinProgress_i='1' else s_dtackOE;
VME_DATA_DIR_o <= '1' when IACKinProgress_i='1' else s_dataDir;
VME_DATA_OE_o <= '1' when IACKinProgress_i='1' else s_dataOE;
VME_ADDR_DIR_o <= s_addrDir;
VME_ADDR_OE_o <= s_addrOE;
......@@ -504,7 +505,7 @@ begin
s_dataOE <= '0';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -532,7 +533,7 @@ begin
s_dataOE <= '0';
s_addrDir <= '0';
s_addrOE <= '0';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -548,12 +549,14 @@ begin
s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
if s_cardSel='1' and s_transferType=LCK then -- LOCK request
if s_lockSel='1' then -- LOCK request
s_mainFSMstate <= ACKNOWLEDGE_LOCK;
elsif s_addressingType=TWOedge then -- start 2e transfer
s_mainFSMstate <= WAIT_FOR_DS_2e;
elsif s_confAccess='1' or (s_cardSel='1' and WBbusy_i='0') then -- If this slave is addressed, start transfer
s_mainFSMstate <= WAIT_FOR_DS;
else
s_mainFSMstate <= DECODE_ACCESS;
end if;
when WAIT_FOR_DS =>
......@@ -562,7 +565,7 @@ begin
s_dataOE <= '0';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -590,7 +593,7 @@ begin
s_dataOE <= '0';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '1';
s_incrementAddr <= '0';
......@@ -614,7 +617,7 @@ begin
s_dataOE <= '0';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -644,7 +647,7 @@ begin
s_dataOE <= '1';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrOE <= '1';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '1';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -674,7 +677,7 @@ begin
s_dataOE <= '1';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrOE <= '1';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -731,7 +734,7 @@ begin
s_dataOE <= '0';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -763,7 +766,7 @@ begin
s_dataOE <= '0';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '1';
......@@ -787,7 +790,7 @@ begin
s_dataOE <= '0';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -814,7 +817,7 @@ begin
if VME_DS_n_oversampled /= "11" then
s_mainDTACK <= '0';
else
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
end if;
s_memReq <= '0';
s_DSlatch <= '0';
......@@ -839,7 +842,7 @@ begin
s_dataOE <= '1';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -865,7 +868,7 @@ begin
s_dataOE <= '1';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -889,7 +892,7 @@ begin
s_dataOE <= '1';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -971,7 +974,7 @@ begin
s_dataOE <= '1';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -997,7 +1000,7 @@ begin
s_dataOE <= '1';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -1155,7 +1158,7 @@ begin
s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
if readFIFOempty_i='0' and s_2eType=TWOe_SST then
if readFIFOempty_i='0' then--and s_2eType=TWOe_SST then
s_mainFSMstate <= TWOe_FIFO_READ;
end if;
......@@ -1217,7 +1220,7 @@ begin
s_dataOE <= '0';
s_addrDir <= '0';
s_addrOE <= '0';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -1291,7 +1294,7 @@ begin
s_dataOE <= '0';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= 'Z';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
......@@ -1367,7 +1370,8 @@ lock_o <= s_lock;
-- DTACK multiplexing
VME_DTACK_n_o <= irqDTACK_i when IACKinProgress_i='1' else
s_mainDTACK;
'0' when s_mainDTACK='0' else
'Z';
-- Bidirectional signal handling
......@@ -1674,6 +1678,8 @@ memReq_o <= s_memReq and s_cardSel; -- memory request to WB only if
-- Access decode (NOTE: since A64 is supported, there are 4 64-bit FUNC_ADERs, because two consecutive 32-bit FUNC_ADERs are needed to decode a 64 bit address)
s_cardSel <= '1' when s_moduleEnable='1' and (((s_funcMatch(3)='1' and s_AMmatch(3)='1') or (s_funcMatch(2)='1' and s_AMmatch(2)='1') or (s_funcMatch(1)='1' and s_AMmatch(1)='1') or (s_funcMatch(0)='1' and s_AMmatch(0)='1'))) and s_addressingType/=CR_CSR and s_initInProgress='0' else '0'; -- NOTE: addressing any of the 4 functions will result in s_cardSel='1' (and the address and data will be forwarded to the WB bus), therefore the WB slave must decode the address by itself, if it wishes to implement different functions.
s_lockSel <= '1' when s_moduleEnable='1' and s_initInProgress='0' and s_transferType=LCK and (s_funcMatch(3)='1' or s_funcMatch(2)='1' or s_funcMatch(1)='1' or s_funcMatch(0)='1') else '0';
s_confAccess <= '1' when s_CSRarray(BAR)(7 downto 3)=s_locAddr(23 downto 19) and s_addressingType=CR_CSR and s_initInProgress='0' else '0'; -- CR/CSR decode
......@@ -2121,7 +2127,9 @@ s_CSRdata <= s_CSRarray(BAR) when s_CrCsrOffsetAddr=BAR_addr
s_CSRarray(FUNC0_ADER_3) when s_CrCsrOffsetAddr=FUNC0_ADER_3_addr else
s_CSRarray(IRQ_ID) when s_CrCsrOffsetAddr=IRQ_ID_addr else
s_CSRarray(IRQ_level) when s_CrCsrOffsetAddr=IRQ_level_addr;
IRQlevelReg_o <= s_CSRarray(IRQ_level);
-- Initialization procedure
......
HDL/VME64e_ActHDL_src/WB_bus.vhd
View file @ 14081a92
......@@ -44,7 +44,6 @@ entity WB_bus is
ACK_i: in std_logic;
WE_o: out std_logic;
STALL_i: in std_logic;
IRQ_i: in std_logic;
memReq_i: in std_logic;
memAck_o: out std_logic;
......@@ -54,7 +53,6 @@ entity WB_bus is
sel_i: in std_logic_vector(7 downto 0);
RW_i: in std_logic;
lock_i: in std_logic;
IRQ_o: out std_logic;
err_o: out std_logic;
rty_o: out std_logic;
cyc_i: in std_logic;
......@@ -64,7 +62,8 @@ entity WB_bus is
FIFOrden_o: out std_logic;
FIFOwren_o: out std_logic;
FIFOdata_i: in std_logic_vector(63 downto 0);
FIFOdata_o: out std_logic_vector(63 downto 0);
FIFOdata_o: out std_logic_vector(63 downto 0);
FIFOreset_o: out std_logic;
writeFIFOempty_i: in std_logic;
TWOeInProgress_i: in std_logic;
WBbusy_o: out std_logic
......@@ -98,7 +97,15 @@ signal s_ackCountEnd: std_logic; -- marks that all
signal s_FIFOrden: std_logic; -- FIFO read enable
type t_2eFSMstates is (IDLE, ADDR_LATCH, SET_CONTROL_SIGNALS, DO_PIPELINED_COMM, WAIT_FOR_END);
signal s_FIFOreset, s_FIFOreset_1, s_FIFOreset_2: std_logic; -- Resets FIFO at the end of each transfer
type t_2eFSMstates is ( IDLE,
ADDR_LATCH,
SET_CONTROL_SIGNALS,
DO_PIPELINED_COMM,
WAIT_FOR_END,
FIFO_RESET
);
signal s_2eFSMstate: t_2eFSMstates;
begin
......@@ -132,14 +139,15 @@ DAT_o <= locData_i when s_FSMactive='0' else FIFOdata_i;
ADR_o <= locAddr_i when s_FSMactive='0' else s_locAddr;
WE_o <= not RW_i when s_FSMactive='0' else s_WE;
IRQ_o <= IRQ_i;
LOCK_o <= lock_i;
err_o <= ERR_i when s_FSMactive='0' else '0';
rty_o <= RTY_i when s_FSMactive='0' else '0';
SEL_o <= sel_i when s_FSMactive='0' else (others => '1');
CYC_o <= cyc_i when s_FSMactive='0' else s_cyc;
WBbusy_o <= s_FSMactive;
WBbusy_o <= s_FSMactive;
-- 2e FSM
......@@ -153,6 +161,7 @@ begin
s_pipeCommActive <='0';
s_WE <='0';
s_addrLatch <='0';
s_FIFOreset <='0';
s_2eFSMstate <= IDLE;
else
case s_2eFSMstate is
......@@ -163,6 +172,7 @@ begin
s_WE <= not RW_i;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_FIFOreset <='0';
if TWOeInProgress_i='1' then
s_2eFSMstate <= ADDR_LATCH;
end if;
......@@ -173,6 +183,7 @@ begin
s_WE <= s_WE;
s_addrLatch <='1';
s_pipeCommActive <='0';
s_FIFOreset <='0';
s_2eFSMstate <= SET_CONTROL_SIGNALS;
when SET_CONTROL_SIGNALS =>
......@@ -180,7 +191,8 @@ begin
s_cyc <='1';
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_pipeCommActive <='0';
s_FIFOreset <='0';
s_2eFSMstate <= DO_PIPELINED_COMM;
when DO_PIPELINED_COMM =>
......@@ -189,6 +201,7 @@ begin
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='1';
s_FIFOreset <='0';
if s_ackCountEnd='1' then
s_2eFSMstate <= WAIT_FOR_END;
else
......@@ -201,16 +214,27 @@ begin
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_FIFOreset <='0';
if TWOeInProgress_i='0' then
s_2eFSMstate <= IDLE;
s_2eFSMstate <= FIFO_RESET;
end if;
when FIFO_RESET =>
s_FSMactive <='0';
s_cyc <='0';
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_FIFOreset <='1';
s_2eFSMstate <= IDLE;
when OTHERS =>
s_FSMactive <='0';
s_cyc <='0';
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_FIFOreset <='0';
s_2eFSMstate <= IDLE;
end case;
......@@ -313,7 +337,21 @@ end process;
s_FIFOrden <= '1' when s_pipeCommActive='1' and s_WE='1' and STALL_i='0' and writeFIFOempty_i='0' and s_beatCountEnd='0' else '0';
FIFOrden_o <= s_FIFOrden;
FIFOwren_o <= ACK_i when s_pipeCommActive='1' and s_WE='0' else '0';
FIFOwren_o <= ACK_i when s_pipeCommActive='1' and s_WE='0' else '0';
-- FIFO reset
p_FIFOresetStretch: process(clk_i)
begin
if rising_edge(clk_i) then
s_FIFOreset_1 <= s_FIFOreset;
s_FIFOreset_2 <= s_FIFOreset_1;
end if;
end process;
FIFOreset_o <= s_FIFOreset or s_FIFOreset_1 or s_FIFOreset_2;
......
HDL/testbenches/sim_vme64master.vhd
View file @ 14081a92
......@@ -24,7 +24,8 @@
--{entity {sim_vme64master} architecture {sim_vme64master}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_logic_unsigned.all;
......@@ -42,7 +43,16 @@ entity sim_vme64master is
VME_BERR_n_i : in STD_LOGIC;
VME_ADDR_b : inout STD_LOGIC_VECTOR(31 downto 1);
VME_DATA_b : inout STD_LOGIC_VECTOR(31 downto 0);
VME_AM_o : out std_logic_vector(5 downto 0)
VME_AM_o : out std_logic_vector(5 downto 0);
VME_DTACK_OE_i : in std_logic;
VME_DATA_DIR_i : in std_logic;
VME_DATA_OE_i : in std_logic;
VME_ADDR_DIR_i : in std_logic;
VME_ADDR_OE_i : in std_logic;
VME_IRQ_n_i : in STD_LOGIC_VECTOR(6 downto 0);
VME_IACKOUT_n_o : out STD_LOGIC
);
end sim_vme64master;
......@@ -63,6 +73,15 @@ architecture sim_vme64master of sim_vme64master is
signal DATA : std_logic_vector(31 downto 0);
signal AM : std_logic_vector(5 downto 0);
--irq
signal IRQ : std_logic_vector(6 downto 0);
signal IACK : std_logic;
signal s_IRQ_A : std_logic := '0';
signal s_IRQ_ADDR: std_logic_vector(31 downto 1);
signal s_IRQ_DS : std_logic_vector (1 downto 0);
signal s_IRQ_AS : std_logic ;
--control signals
signal s_dataToSend : std_logic_vector(31 downto 0);
signal s_dataToReceive : std_logic_vector(31 downto 0);
......@@ -70,6 +89,7 @@ architecture sim_vme64master of sim_vme64master is
signal s_AM : std_logic_vector(5 downto 0);
type t_dataToTransfer is array (0 to 255) of std_logic_vector(31 downto 0);
signal s_dataToTransfer : t_dataToTransfer;
......@@ -80,76 +100,76 @@ architecture sim_vme64master of sim_vme64master is
signal s_dataTransferType : std_logic_vector(3 downto 0);
--signal s_write : std_logic;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
begin
......@@ -276,9 +296,10 @@ begin
-- make sure to align address properly to reflect AM modes
procedure addressPhase is
begin
assert not (s_AM(5 downto 3) = "110" or s_AM(5 downto 3) = "000") report "only non multiplexed address modes" severity error;
--present address
ADDR(31 downto 1) <= s_address(31 downto 1);
ADDR(31 downto 1) <= s_address(31 downto 1);
DATA <= s_address(63 downto 32);
--present address modifier
AM <= s_AM;
--ADDR(1) <= s_address(0);--s_dataTransferType(1); --set A1
......@@ -424,9 +445,7 @@ begin
AS <= '1';
end writeD32singleMA;
procedure writeGenericBlock(numberOf: integer) is
begin
wait for 100 ns;
......@@ -451,12 +470,11 @@ begin
terminateCycle;
end writeGenericBlock;
procedure readGenericBlock(numberOf: integer) is
begin
wait for 100 ns;
addressPhase;
wait for 10 ns;
--write operation
s_write := '1';
--address the slave
......@@ -478,7 +496,47 @@ begin
terminateCycle;
end readGenericBlock;
--write single 8-32 bit value from bus. this procedure uses non multiplexed addressing
procedure readGenericBlockMBLT(numberOf: integer) is
begin
wait for 100 ns;
s_write := '1'; --read operation
addressPhase; --address the slave
wait for 25 ns;
DS <= s_dataTransferType(3 downto 2);
wait until DTACK = '0';
DS <= "11";
DATA <= (others => 'Z');
ADDR <= (others => 'Z');
LWORD <= 'Z';
wait for 25 ns;
for I in 0 to numberOf loop
if DTACK = '0' then
wait until DTACK /= '0';
end if;
DS <= s_dataTransferType(3 downto 2);
wait until DTACK = '0';
s_dataToTransfer(I) <= VME_data_b; -- save data
s_receivedData(63 downto 33) <= VME_ADDR_b(31 downto 1);
s_receivedData(32) <= VME_LWORD_n_b;
s_receivedData(31 downto 0) <= VME_DATA_b;
report "RECEIVED MBLT DATA: " & hstr(s_receivedData);
wait for 10ns;
DS <= "11"; --rise strobe
end loop;
terminateCycle;
end readGenericBlockMBLT;
--write single 8-32 bit value from bus.
--avaible address modes A16,A24,A32
--
--make sure to set up --s_dataTransferTypeSelect <= D32;
......@@ -489,7 +547,7 @@ begin
s_write := '0'; --it's a write op
addressPhase;
DS <= s_dataTransferType(3 downto 2);
DATA <= s_dataToSend;
DATA <= s_dataToSend;
--assert DTACK = '1' report "DTACK should not be low here" severity error;
wait until DTACK = '0'; --wait for ack
......@@ -498,7 +556,7 @@ begin
terminateCycle;
end writeGenericSingle;
--read single 8-32 bit value from bus. this procedure uses non multiplexed addressing
--read single 8-32 bit value from bus.
--avaible address modes A16,A24,A32
--
--make sure to set up --s_dataTransferTypeSelect <= D32;
......@@ -510,6 +568,7 @@ begin
wait for 20ns; --addressing
s_write := '1'; -- read op
addressPhase;
--addressPhaseMultiplexed;
DS <= s_dataTransferType(3 downto 2);
......@@ -525,7 +584,40 @@ begin
terminateCycle;
end readGenericSingle;
end readGenericSingle;
--same as read generic single, but with address pipelining
procedure readGenericSingleAP(check:boolean ) is
begin
wait for 20ns; --addressing
s_write := '1'; -- read op
addressPhase;
--addressPhaseMultiplexed;
DS <= s_dataTransferType(3 downto 2);
DATA <= (others => 'Z'); --input on data
wait until DTACK = '0'; --wait for data
s_address <= s_address +4;
wait for 1ns;
ADDR(31 downto 1) <= s_address(31 downto 1);
--read data
if check = true then
assert s_dataToReceive = VME_DATA_b report "did not receive expected data" severity failure;
end if;
s_receivedData(31 downto 0) <= VME_DATA_b;
wait for 20ns;--simulate reading delay
AS <= '1','0' after 25ns;
wait until DTACK = '0'; --wait for data
s_receivedData(31 downto 0) <= VME_DATA_b;
wait for 20ns;--simulate reading delay
terminateCycle;
end readGenericSingleAP;
--try to configure the bus
......@@ -534,41 +626,52 @@ begin
s_dataTransferTypeSelect <= D08O;
s_AM <= "101111"; --set AM to CR/CSR access
-- s_address(32 downto 1) <= x"00000081";
-- s_address(31 downto 0) <= x"00000623";--adem 0
-- report "reading adem";
-- readGenericSingle(false);
-- s_address(31 downto 0) <= x"00000627";--adem 1
-- readGenericSingle(false);
-- s_address(32 downto 1) <= x"00000123";
-- s_address(31 downto 0) <= x"0000062B";--adem 2
-- readGenericSingle(false);
--
s_address(31 downto 0) <= x"00000623";--adem 0
report "reading adem";
--readGenericBlock(4);
-- s_address(31 downto 0) <= x"0000062F";--adem 3
-- readGenericSingle(false);
readGenericSingle(false);
s_address(31 downto 0) <= x"00000627";--adem 1
readGenericSingle(false);
s_address(31 downto 0) <= x"0000062B";--adem 2
readGenericSingle(false);
s_address(31 downto 0) <= x"0000062F";--adem 3
readGenericSingle(false);
--
s_address(31 downto 0) <= x"0007ff63";--ader 0
s_dataToSend <= x"00000007";
-------CONFIG ADER 0 ------
s_address(31 downto 0) <= x"0007ff63";--ader 0-0
s_dataToSend <= x"00000077";
writeGenericSingle;
s_address(31 downto 0) <= x"0007ff67";--ader 0
s_address(31 downto 0) <= x"0007ff67";--ader 0-1
s_dataToSend <= x"000000f0";
writeGenericSingle;
s_address(31 downto 0) <= x"0007ff6f";--ader 3
s_dataToSend <= x"000000f4";
--s_dataToSend <= x"00000034";
s_address(31 downto 0) <= x"0007ff6f";--ader 0-3
--s_dataToSend <= x"000000e0";--a24 mblt
--s_dataToSend <= x"00000004";--a64
--s_dataToSend <= x"0000000C";--a64 blt
--s_dataToSend <= x"00000000";--a64 mblt
--s_dataToSend <= x"000000fc";--a24 blt
--s_dataToSend <= x"00000034";--a32
--s_dataToSend <= x"00000030";--a32 mblt
--s_dataToSend <= x"00000020";--a32 mblt
--s_dataToSend <= x"00000005";--xam a32 xam:0x01
--s_dataToSend <= x"00000009";--xam a64 xam:0x02
s_dataToSend <= x"00000045";--xam a32/d64 sst xam:0x11
--s_dataToSend <= x"00000049";--xam a64/d64 sst xam:0x12
writeGenericSingle;
--s_address(31 downto 0) <= x"0007ff63";--ader 0
----CONFIG IRQ REGISTERS----
s_address(31 downto 0) <= x"0007FBFB"; --set IRQ level
s_dataToSend <= x"00000002"; --set it to line 2
writeGenericSingle;
--readGenericSingle(false);
--s_dataToReceive <= s_dataToSend;
--s_dataToReceive(31 downto 8) <= (others => 'Z');
--readGenericSingle(true);
s_address(31 downto 0) <= x"0007FBFF"; --set IRQ id
s_dataToSend <= x"000000AB"; --set it to 0xAB
writeGenericSingle;
-----ENABLE MODULE----------------
s_address(31 downto 0) <= x"0007fffb";
s_dataToSend <= x"00000010"; --enable module
writeGenericSingle;
......@@ -579,11 +682,13 @@ begin
report "end configuration";
end procedure;
procedure testCram is
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
variable BEG_CRAM:std_logic_vector(23 downto 0);
variable END_CRAM:std_logic_vector(23 downto 0);
procedure testCram is
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
variable BEG_CRAM:std_logic_vector(23 downto 0);
variable END_CRAM:std_logic_vector(23 downto 0);
begin
s_AM <= "101111"; --set AM to CR/CSR access
s_dataTransferTypeSelect <= D08O;
......@@ -621,7 +726,7 @@ begin
--TEST no1: writing to CRAM
s_AM <= "101111"; --set AM to CR/CSR access
--BEG_CRAM := BEG_CRAM -1; --must fail!!! uncomment to test
s_address(23 downto 0) <= BEG_CRAM;
......@@ -650,137 +755,424 @@ begin
end procedure;
begin
procedure read2e(numberOf:integer) is
begin
--addressing phase 1
WRITE <= '1';
AM <= "100000"; --0x20 xam
AS <='0';
wait for 25ns;
ADDR(7 downto 1) <= (others => '0');
LWORD <= '1'; --a32/d64
--ADDR(1) <= '1'; --a64/d64
--LWORD <= '0'; --a64/d64
ADDR(31 downto 8) <= s_address(31 downto 8);
DATA <= s_address(63 downto 32);
DS(0) <= '0';
wait until DTACK = '0';
wait for 10ns;
--end of phase 1
--phase 2
ADDR(7 downto 1) <= s_address(7 downto 1);
LWORD <= s_address(1);
ADDR(15 downto 8) <= x"05"; --beat count
ADDR(31 downto 15) <= (others => '0');
DATA <= (others => '0');
DS(0) <= '1';
wait until DTACK = 'Z';
--end of phase 2
--phase 3
DS(0) <= '0';
wait until DTACK <= '0';
--end of phase 3
-- end of addressing !!!
--relaes data and address lines!
LWORD <= 'Z';
ADDR <= (others => 'Z');
DATA <= (others => 'Z');
wait for 10ns;
for I in 0 to numberOf-1 loop
DS(1) <= '0';
wait until DTACK <= 'Z';
s_receivedData(63 downto 33) <= VME_ADDR_b(31 downto 1);
s_receivedData(32) <= VME_LWORD_n_b;
s_receivedData(31 downto 0) <= VME_DATA_b;
report "RECEIVED MBLT DATA: " & hstr(s_receivedData);
wait for 10ns; --sim reading delay
DS(1) <= '1';
wait until DTACK <='0';
s_receivedData(63 downto 33) <= VME_ADDR_b(31 downto 1);
s_receivedData(32) <= VME_LWORD_n_b;
s_receivedData(31 downto 0) <= VME_DATA_b;
report "RECEIVED MBLT DATA: " & hstr(s_receivedData);
wait for 10ns;
end loop;
DS <= "11";
terminateCycle;
end procedure read2e;
procedure read2eSST(numberOf:integer) is
variable dataToReceive : std_logic_vector(63 downto 0);
variable xam : std_logic_vector (7 downto 0);
begin
--addressing phase 1
--ADDR <= (others => '0');
WRITE <= '1'; --read!
AM <= "100000"; --0x20 xam
AS <='0';
wait for 25ns;
xam := x"11"; --a32/d64
--xam := x"12"; --a64/d64
--xam <= 0x21 --a32/d64 broadcast
--xam <= 0x22 --a32/d64 broadcast
ADDR(7 downto 1) <= xam(7 downto 1);
LWORD <= xam(0);
ADDR(31 downto 8) <= s_address(31 downto 8);
DATA <= s_address(63 downto 32);
DS(0) <= '0';
wait until DTACK = '0';
wait for 10ns;
--end of phase 1
--phase 2
ADDR(7 downto 1) <= s_address(7 downto 1);
LWORD <= s_address(1);
ADDR(15 downto 8) <= x"0A"; --beat count
ADDR(31 downto 15) <= (others => '0');
DATA <= (others => '0');
DATA(3 downto 0) <= x"2";
DS(0) <= '1';
wait until DTACK = 'Z';
--end of phase 2
--phase 3
DS(0) <= '0';
wait until DTACK <= '0';
--end of phase 3
-- end of addressing !!!
--relaes data and address lines!
LWORD <= 'Z';
ADDR <= (others => 'Z');
DATA <= (others => 'Z');
wait for 10ns;
wait for 50 ns;
for I in 0 to 3 loop
DS(1) <= '0';
wait until DTACK /= '0';
dataToReceive(63 downto 33) := VME_ADDR_B;
dataToReceive(32) := VME_LWORD_n_b;
dataToReceive(31 downto 0) := VME_DATA_b;
report "data:" & hstr(dataToReceive);
wait until DTACK /= '1';
dataToReceive(63 downto 33) := VME_ADDR_B;
dataToReceive(32) := VME_LWORD_n_b;
dataToReceive(31 downto 0) := VME_DATA_b;
report "data:" & hstr(dataToReceive);
end loop;
DS <= "11";
terminateCycle;
end procedure read2eSST;
procedure write2e(numberOf:integer) is
variable dataToSend : std_logic_vector(63 downto 0);
begin
--addressing phase 1
WRITE <= '0'; --write!
AM <= "100000"; --0x20 xam
AS <='0';
wait for 25ns;
ADDR(7 downto 1) <= (others => '0');
LWORD <= '1'; --a32/d64
--ADDR(1) <= '1'; --a64/d64
--LWORD <= '0'; --a64/d64
ADDR(31 downto 8) <= s_address(31 downto 8);
DATA <= s_address(63 downto 32);
DS(0) <= '0';
wait until DTACK = '0';
wait for 10ns;
--end of phase 1
--phase 2
ADDR(7 downto 1) <= s_address(7 downto 1);
LWORD <= s_address(1);
ADDR(15 downto 8) <= x"05"; --beat count
ADDR(31 downto 15) <= (others => '0');
DATA <= (others => '0');
DS(0) <= '1';
wait until DTACK = 'Z';
--end of phase 2
--phase 3
DS(0) <= '0';
wait until DTACK <= '0';
--end of phase 3
-- end of addressing !!!
--relaes data and address lines!
LWORD <= 'Z';
ADDR <= (others => 'Z');
DATA <= (others => 'Z');
wait for 10ns;
dataToSend := x"0123456789ABC001";
for I in 0 to numberOf loop
wait for 10ns;
ADDR <= dataToSend(63 downto 33);
LWORD <= dataToSend(32);
DATA <= dataToSend(31 downto 0);
DS(1) <= '0';
wait until DTACK <= 'Z'; --odd end
dataToSend := dataToSend +1;
wait for 10ns;
ADDR <= dataToSend(63 downto 33);
LWORD <= dataToSend(32);
DATA <= dataToSend(31 downto 0);
DS(1) <= '1';
wait until DTACK <='0'; --even end
dataToSend := dataToSend +1;
end loop;
DS <= "11";
terminateCycle;
end procedure write2e;
procedure write2eSST(numberOf:integer) is
variable dataToSend : std_logic_vector(63 downto 0);
variable xam : std_logic_vector (7 downto 0);
begin
--addressing phase 1
ADDR <= (others => '0');
WRITE <= '0'; --write!
AM <= "100000"; --0x20 xam
AS <='0';
wait for 25ns;
xam := x"11"; --a32/d64
--xam := x"12"; --a64/d64
--xam <= 0x21 --a32/d64 broadcast
--xam <= 0x22 --a32/d64 broadcast
ADDR(7 downto 1) <= xam(7 downto 1);
LWORD <= xam(0);
ADDR(31 downto 8) <= s_address(31 downto 8);
DATA <= s_address(63 downto 32);
DS(0) <= '0';
wait until DTACK = '0';
wait for 10ns;
--end of phase 1
--phase 2
ADDR(7 downto 1) <= s_address(7 downto 1);
LWORD <= s_address(1);
ADDR(15 downto 8) <= x"0A"; --beat count
ADDR(31 downto 15) <= (others => '0');
DATA <= (others => '0');
DATA(3 downto 0) <= x"2";
DS(0) <= '1';
wait until DTACK = 'Z';
--end of phase 2
--phase 3
DS(0) <= '0';
wait until DTACK <= '0';
--end of phase 3
-- end of addressing !!!
--relaes data and address lines!
LWORD <= 'Z';
ADDR <= (others => 'Z');
DATA <= (others => 'Z');
wait for 10ns;
dataToSend := x"0123456789ABC001";
wait for 50 ns;
for I in 0 to 4 loop
--wait for 12ns;
ADDR <= dataToSend(63 downto 33);
LWORD <= dataToSend(32);
DATA <= dataToSend(31 downto 0);
wait for 12ns;
DS(1) <= '0';
wait for 12ns;
dataToSend := dataToSend +1;
ADDR <= dataToSend(63 downto 33);
LWORD <= dataToSend(32);
DATA <= dataToSend(31 downto 0);
wait for 12ns;
DS(1) <= '1';
wait for 12ns;
dataToSend := dataToSend +1;
end loop;
DS <= "11";
terminateCycle;
end procedure write2eSST;
----------------------------------------------------
--------------TEST PROCEDURES START-----------------
----------------------------------------------------
begin
--execute
wait for 70 ns;
configBus;
wait for 200 ns;
s_AM <= "111101"; --A24 data access blt
--s_AM <= "111101"; --A24 data access blt
--s_AM <= "111111"; --A24 data access
s_AM <= "000001"; --A64 data access
--s_AM <= "000011"; --A64 data access blt
--s_AM <= "000000"; --A64 data access mblt
--s_AM <= "001101"; --A32 data access
s_dataTransferTypeSelect <= D32_BLOCK;
--s_AM <= "001100"; --A32 data access mblt
--s_AM <= "001000"; --A32 data access mblt
--s_dataTransferTypeSelect <= D32;
s_address(63 downto 0) <= (others => '0');
wait for 10ns;
s_address(31 downto 0) <= x"77f00004";--x"0003fffd";
s_address(31 downto 0) <= x"00f00004";--x"0003fffd";
--s_address <= x"00ff00ff77f00004";--x"0003fffd";
s_dataToSend <= x"00001110";
writeGenericSingle;
readGenericSingle(false);
wait;
--s_AM <= "111111"; --A24 data access blt
s_address(32 downto 1) <= x"07000020";--x"0003fffd";
--readGenericBlock(5);
writeGenericBlock(5);
wait for 500 ns;
--
-- -----2eVME test suite ----
-- write2e(5);
-- wait for 200 ns;
-- read2e(5);
-- --------------------------
write2eSST(5);
wait for 200ns;
--read2eSST(5);
wait;
--readGenericBlock(5);
--writeGenericBlock(5);
s_AM <= "101111"; --set AM to CR/CSR access
s_dataTransferTypeSelect <= D08O;
s_address(31 downto 0) <= x"0007fffb";
readGenericSingle(false);
report "received data" & hstr(s_receivedData);
s_dataToSend(7 downto 0) <= "00010000"; --enable module
writeGenericSingle;
readGenericSingle(false);
report "received data" & hstr(s_receivedData);
--read2eSST(10);
--write2eSST(10);
wait for 30 ns;
write2eSST(10);
wait for 30 ns;
write2eSST(10);
--read2e(100);
wait;
--testCram;
--configBus;
report "accessing data";
--s_AM <= "111101"; --A24 data access
s_AM <= "001101"; --A32 data access
s_dataTransferTypeSelect <= D32;
s_address(32 downto 1) <= x"7F800000";--x"0003fffd";
s_dataToSend <= x"00000010";
readGenericSingle(false);
wait;
writeGenericBlock(5);
readGenericSingle(false);
readGenericSingleAP(false);
writeGenericSingle;
wait;
testReservedAms;
readD32single;
wait;
readGenericBlock(5);
readGenericSingle(false);
wait;
--s_AM <= "111111"; --A24 data access blt
s_address(32 downto 1) <= x"00f0000f";--x"0003fffd";
--readGenericBlock(5);
writeGenericBlock(5);
end process;
--
----process used for simulating slave block write
-- dtackproc: process
-- begin
-- DTACK <= '1';
-- wait for 100 ns;
-- wait until AS = '0';
--
-- loop
-- wait until DS = "00";
-- wait for 75 ns;
-- --write data
-- DTACK <= '0';
-- wait until DS = "11";
-- wait for 25ns;
-- DTACK <= '1';
-- end loop;
--
-- wait until DS = "11";
-- DTACK <= '1';
-- --DATA <= (others => 'Z');
-- end process;
-- dtackproc: process
-- begin
-- loop
-- DATA <= (others => 'Z');
-- DTACK <= '1';
-- wait for 10 ns;
-- wait until AS = '0';
-- --end of address
--
-- loop
-- --wait for data
-- if not DS="00" then wait until DS = "00"; end if;
-- if(WRITE = '0') then
-- report "new data";
-- else
-- DATA <= x"01234567";
-- end if;
-- wait for 75 ns; --simulate reading/writing
-- --send ack
-- DTACK <= '0';
-- if not DS="11" then wait until DS = "11"; end if;
-- wait for 25ns;
-- DTACK <= '1';
-- wait for 10ns;
--
-- if AS='1' then
-- report "exiting";
-- exit;
-- end if;
--
-- end loop;
-- end loop;
--
-- end process;
end process;
IRQ_ACK: process
begin
IACK <= '1';
wait until IRQ(1) = '0';
--wait for 3050ns;
report "INTERRUPT TRIGGERED";
s_IRQ_A <= '1';
s_IRQ_DS <= "11";
s_IRQ_AS <= '1';
s_IRQ_ADDR <= (others => '0');
wait for 1ns;
s_IRQ_ADDR(3 downto 1) <= "010";
IACK <= '0';
s_IRQ_AS <= '0';
--s_IRQ_DS <= "10";
wait for 10 ns;
s_IRQ_DS <= "00";
wait until DTACK = '0';
s_IRQ_A <= '0';
end process;
......@@ -789,23 +1181,50 @@ begin
-----------------------------------
---------CONNECTIONS---------------
-----------------------------------
VME_AS_n_i <= AS;
VME_AS_n_i <=s_IRQ_AS when s_IRQ_A = '1' else AS;
VME_LWORD_n_b <= LWORD;
--LWORD <= VME_LWORD_n_b;
RETRY <= VME_RETRY_n_i;
VME_WRITE_n_o <= WRITE;
VME_DS_n_o <= DS;
VME_DS_n_o <= s_IRQ_DS when S_IRQ_A = '1' else DS;
--VME_GA_i : in STD_LOGIC_VECTOR(4 downto 0);
DTACK <= VME_DTACK_n_i;
BERR <= VME_BERR_n_i;
VME_ADDR_b <= ADDR;
VME_ADDR_b <= s_IRQ_ADDR when S_IRQ_A= '1' else ADDR;
--ADDR <= VME_ADDR_b;
VME_DATA_b <= DATA;
--DATA <= VME_DATA_b;
VME_AM_o <= AM;
IRQ <= VME_IRQ_n_i;
VME_IACKOUT_n_o <= IACK;
end sim_vme64master;
latchIcDtackCheck: process
begin
wait until DTACK = '0';
assert VME_DTACK_OE_i = '1' REPORT "DTACK is '0' but LATCH ic is NOT enabled" severity failure;
end process;
--assert VME_DTACK_OE_i = '1' and DTACK /= 'Z' report "DTACK is '0' but LATCH ic is NOT enabled" severity failure;
-- latchIcDtackCheck1: process
-- begin
-- wait until VME_DTACK_OE_i = '1';
-- wait for 10ns;
-- assert DTACK = '0' REPORT "DTACK is not '0' but LATCH ic is enabled" severity failure;
-- end process;
--
-- VME_DATA_DIR_i : in std_logic;
-- VME_DATA_OE_i : in std_logic;
-- VME_ADDR_DIR_i : in std_logic;
-- VME_ADDR_OE_i : in std_logic;
end sim_vme64master;
\ No newline at end of file
HDL/testbenches/sim_wbSlave.vhd
View file @ 14081a92
......@@ -33,17 +33,18 @@ entity sim_wbSlave is
DAT_i: in std_logic_vector(63 downto 0);
DAT_o: out std_logic_vector(63 downto 0);
ADR_i: in std_logic_vector(63 downto 0);
TGA_i: in std_logic_vector(3 downto 0);
TGC_i: in std_logic_vector(3 downto 0);
--TGA_i: in std_logic_vector(3 downto 0);
--TGC_i: in std_logic_vector(3 downto 0);
CYC_i: in std_logic;
ERR_o: out std_logic;
LOCK_i: in std_logic;
RTY_o: out std_logic;
SEL_i: in std_logic_vector(7 downto 0);
STB_i: in std_logic;
ACK_o: out std_logic;
ACK_o: out std_logic := '0';
WE_i: in std_logic;
IRQ_o: out std_logic_vector(6 downto 0)
STALL_o : out std_logic;
IRQ_o: out std_logic
);
end sim_wbSlave;
......@@ -55,6 +56,9 @@ signal s_ram : t_ram;
signal s_selectedData : std_logic_vector(63 downto 0);
signal s_stb_count : integer := 0;
signal s_sendCount : std_logic_vector(3 downto 0) := "0000";
begin
......@@ -62,25 +66,73 @@ begin
ERR_o <= '0';
RTY_o <= '0';
--ACK_o <= '1' when STB_i = '1';
fakeInterruot: process
begin
IRQ_o <= '0';
wait for 3500ns;
IRQ_o <= '1','0' after 50 ns;
wait;
end process;
fakeReadWrite: process
begin
if(CYC_i = '0') then wait until CYC_i = '1'; end if;
--ACK_o <= '0';
--if(CYC_i = '0') then wait until CYC_i = '1'; end if;
wait until STB_i = '1';
if STB_i /= '1' then wait until STB_i = '1'; end if;
wait until clk_i = '1';
if(WE_i = '1') then
s_ram(CONV_INTEGER(ADR_i(9 downto 0))) <= DAT_i;
report "saving data";
else
DAT_o <= s_ram(CONV_INTEGER(ADR_i(9 downto 0)));
--DAT_o <= s_ram(CONV_INTEGER(ADR_i(9 downto 0)));
end if;
wait for 10ns;
ACK_o <= '1', '0' after 10ns;
--wait for 10ns;
--ACK_o <= '1', '0' after 1ns;
end process;
DAT_o(63 downto 4) <= x"012345670123456";
DAT_o(3 downto 0) <= s_sendCount;
fakeAckReply: process
variable ack_counter : integer := 0;
begin
if(ack_counter /= s_stb_count) then
ACK_o <= '1', '0' after 1ns;
ack_counter := ack_counter +1 ;
s_sendCount <= s_sendCount +1;
end if;
wait for 30ns;
end process;
fakeSTALL: process
begin
STALL_o <= '0';
if s_stb_count = 5 then
--STALL_o <= '1','0' after 50ns; ---uncomment to test if stall works..
wait for 50ns;
end if;
wait for 1ns;
end process;
stbCounter: process(clk_i)
begin
if rising_edge(clk_i) then
if(STB_i = '1') then
s_stb_count <= s_stb_count +1;
end if;
end if;
end process;
--
end sim_wbSlave;
HDL/testbenches/vme64xcore_top_TB.vhd
View file @ 14081a92
......@@ -26,13 +26,20 @@ architecture TB_ARCHITECTURE of vme64xcore_top_tb is
VME_BBSY_n_i : in STD_LOGIC;
VME_IRQ_n_o : out STD_LOGIC_VECTOR(6 downto 0);
VME_IACKIN_n_i : in STD_LOGIC;
VME_IACKOUT_n_o : out STD_LOGIC;
VME_IACKOUT_n_o : out STD_LOGIC;
VME_DTACK_OE_o: out std_logic;
VME_DATA_DIR_o: out std_logic;
VME_DATA_OE_o: out std_logic;
VME_ADDR_DIR_o: out std_logic;
VME_ADDR_OE_o: out std_logic;
RST_i : in STD_LOGIC;
DAT_i : in STD_LOGIC_VECTOR(63 downto 0);
DAT_o : out STD_LOGIC_VECTOR(63 downto 0);
ADR_o : out STD_LOGIC_VECTOR(63 downto 0);
TGA_o : out STD_LOGIC_VECTOR(3 downto 0);
TGC_o : out STD_LOGIC_VECTOR(3 downto 0);
--TGA_o : out STD_LOGIC_VECTOR(3 downto 0);
--TGC_o : out STD_LOGIC_VECTOR(3 downto 0);
CYC_o : out STD_LOGIC;
ERR_i : in STD_LOGIC;
LOCK_o : out STD_LOGIC;
......@@ -41,26 +48,37 @@ architecture TB_ARCHITECTURE of vme64xcore_top_tb is
STB_o : out STD_LOGIC;
ACK_i : in STD_LOGIC;
WE_o : out STD_LOGIC;
IRQ_i : in STD_LOGIC_VECTOR(6 downto 0) );
STALL_i: in std_logic;
IRQ_i : in STD_LOGIC);
end component;
-- Component declaration of the "sim_vme64master(sim_vme64master)" unit defined in
-- file: "./../../testbenches/sim_vme64master.vhd"
component sim_vme64master
port(
clk_i : in STD_LOGIC;
VME_AS_n_i : out STD_LOGIC;
VME_LWORD_n_b : inout STD_LOGIC;
VME_RETRY_n_i : in STD_LOGIC;
VME_WRITE_n_o : out STD_LOGIC;
VME_DS_n_o : out STD_LOGIC_VECTOR(1 downto 0);
VME_DTACK_n_i : in STD_LOGIC;
VME_BERR_n_i : in STD_LOGIC;
VME_ADDR_b : inout STD_LOGIC_VECTOR(31 downto 1);
VME_DATA_b : inout STD_LOGIC_VECTOR(31 downto 0);
VME_AM_o : out STD_LOGIC_VECTOR(5 downto 0));
port(
clk_i : in STD_LOGIC;
VME_AS_n_i : out STD_LOGIC;
VME_LWORD_n_b : inout STD_LOGIC;
VME_RETRY_n_i : in STD_LOGIC;
VME_WRITE_n_o : out STD_LOGIC;
VME_DS_n_o : out STD_LOGIC_VECTOR(1 downto 0);
VME_DTACK_n_i : in STD_LOGIC;
VME_BERR_n_i : in STD_LOGIC;
VME_ADDR_b : inout STD_LOGIC_VECTOR(31 downto 1);
VME_DATA_b : inout STD_LOGIC_VECTOR(31 downto 0);
VME_AM_o : out STD_LOGIC_VECTOR(5 downto 0);
VME_IRQ_n_i : in STD_LOGIC_VECTOR(6 downto 0);
VME_DTACK_OE_i: in std_logic;
VME_DATA_DIR_i: in std_logic;
VME_DATA_OE_i: in std_logic;
VME_ADDR_DIR_i: in std_logic;
VME_ADDR_OE_i: in std_logic;
VME_IACKOUT_n_o : out STD_LOGIC);
end component;
for all: sim_vme64master use entity work.sim_vme64master(sim_vme64master);
-- Component declaration of the "sim_wbslave(sim_wbslave)" unit defined in
-- file: "./../../testbenches/sim_wbslave.vhd"
......@@ -71,8 +89,8 @@ architecture TB_ARCHITECTURE of vme64xcore_top_tb is
DAT_i : in STD_LOGIC_VECTOR(63 downto 0);
DAT_o : out STD_LOGIC_VECTOR(63 downto 0);
ADR_i : in STD_LOGIC_VECTOR(63 downto 0);
TGA_i : in STD_LOGIC_VECTOR(3 downto 0);
TGC_i : in STD_LOGIC_VECTOR(3 downto 0);
--TGA_i : in STD_LOGIC_VECTOR(3 downto 0);
--TGC_i : in STD_LOGIC_VECTOR(3 downto 0);
CYC_i : in STD_LOGIC;
ERR_o : out STD_LOGIC;
LOCK_i : in STD_LOGIC;
......@@ -80,8 +98,9 @@ architecture TB_ARCHITECTURE of vme64xcore_top_tb is
SEL_i : in STD_LOGIC_VECTOR(7 downto 0);
STB_i : in STD_LOGIC;
ACK_o : out STD_LOGIC;
WE_i : in STD_LOGIC;
IRQ_o : out STD_LOGIC_VECTOR(6 downto 0));
WE_i : in STD_LOGIC;
STALL_o : out STD_LOGIC;
IRQ_o : out STD_LOGIC);
end component;
for all: sim_wbslave use entity work.sim_wbslave(sim_wbslave);
......@@ -100,7 +119,8 @@ architecture TB_ARCHITECTURE of vme64xcore_top_tb is
signal ERR_i : STD_LOGIC;
signal RTY_i : STD_LOGIC;
signal ACK_i : STD_LOGIC;
signal IRQ_i : STD_LOGIC_VECTOR(6 downto 0);
signal IRQ_i : STD_LOGIC;
signal STALL_i : STD_LOGIC;
signal VME_LWORD_n_b : STD_LOGIC;
signal VME_ADDR_b : STD_LOGIC_VECTOR(31 downto 1);
signal VME_DATA_b : STD_LOGIC_VECTOR(31 downto 0);
......@@ -120,6 +140,12 @@ architecture TB_ARCHITECTURE of vme64xcore_top_tb is
signal STB_o : STD_LOGIC;
signal WE_o : STD_LOGIC;
signal VME_DTACK_OE_o:std_logic;
signal VME_DATA_DIR_o:std_logic;
signal VME_DATA_OE_o:std_logic;
signal VME_ADDR_DIR_o: std_logic;
signal VME_ADDR_OE_o:std_logic;
-- Add your code here ...
begin
......@@ -141,6 +167,13 @@ begin
VME_ADDR_b => VME_ADDR_b,
VME_DATA_b => VME_DATA_b,
VME_BBSY_n_i => VME_BBSY_n_i,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_OE_o => VME_DATA_OE_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_o => VME_ADDR_OE_o,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
......@@ -148,8 +181,8 @@ begin
DAT_i => DAT_i,
DAT_o => DAT_o,
ADR_o => ADR_o,
TGA_o => TGA_o,
TGC_o => TGC_o,
--TGA_o => TGA_o,
--TGC_o => TGC_o,
CYC_o => CYC_o,
ERR_i => ERR_i,
LOCK_o => LOCK_o,
......@@ -158,6 +191,7 @@ begin
STB_o => STB_o,
ACK_i => ACK_i,
WE_o => WE_o,
STALL_i => STALL_i,
IRQ_i => IRQ_i
);
......@@ -173,7 +207,16 @@ begin
VME_BERR_n_i => VME_BERR_n_o,
VME_ADDR_b => VME_ADDR_b,
VME_DATA_b => VME_DATA_b,
VME_AM_o => VME_AM_i
VME_AM_o => VME_AM_i,
VME_DTACK_OE_i => VME_DTACK_OE_o,
VME_DATA_DIR_i => VME_DATA_DIR_o,
VME_DATA_OE_i => VME_DATA_OE_o,
VME_ADDR_DIR_i => VME_ADDR_DIR_o,
VME_ADDR_OE_i => VME_ADDR_OE_o,
VME_IRQ_n_i => VME_IRQ_n_o,
VME_IACKOUT_n_o => VME_IACKIN_n_i
);
stimulGen_wb : sim_wbslave
......@@ -183,8 +226,8 @@ begin
DAT_i => DAT_o,
DAT_o => DAT_i,
ADR_i => ADR_o,
TGA_i => TGA_o,
TGC_i => TGC_o,
--TGA_i => TGA_o,
--TGC_i => TGC_o,
CYC_i => CYC_o,
ERR_o => ERR_i,
LOCK_i => LOCK_o,
......@@ -193,12 +236,17 @@ begin
STB_i => STB_o,
ACK_o => ACK_i,
WE_i => WE_o,
STALL_O => STALL_i,
IRQ_o => IRQ_i
);
clkGen: process
begin
clk_i<='0', '1' after 0.5 ns;
--clk_i<='0', '1' after 0.5 ns;
--wait for 0.5ns;
clk_i <= '0';
wait for 0.5ns;
clk_i <= '1';
wait for 0.5ns;
end process;
......
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