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VME64x core
Commit 14081a92 authored by rstefanic's avatar rstefanic
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git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@22 665b4545-5c6b-4c24-801b-41150b02b44b
parent b36b4ab9
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HDL/VME64e_ActHDL/VME64xCore.wsw
View file @ 14081a92
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\references\VME64_slave_verilog\ga_decoder.v|]
TemplateId=2
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\VME64xCore\src\compile.do|]
TemplateId=6
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\VME64e_ActHDL_src\VME_bus.vhd|]
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\VME64e_ActHDL_src\WB_bus.vhd|]
TemplateId=0
ActiveDocument=1
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\VME64xCore\src\VME_unaligned_test.tcl|]
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\VME64e_ActHDL_src\IRQ_controller.vhd|]
TemplateId=0
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\VME64e_ActHDL_src\VME_bus.vhd|]
TemplateId=0
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\VME64e_ActHDL_src\VME64xCore_Top.vhd|]
TemplateId=0
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\VME64xCore\src\VME_top_test.tcl|]
TemplateId=7
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\VME64xCore\src\compile.do|]
TemplateId=6
[OPENDOC|Aldec.WaveFormASDB.7|.\VME64xCore\src\wave.asdb|]
TemplateId=0
[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\VME64e_ActHDL_src\VME_pack.vhd|]
TemplateId=0
HDL/VME64e_ActHDL/VME64xCore/VME64xCore.LIB
View file @ 14081a92
timestamp=1273754497258
timestamp=1274258923148
[~A]
ModifyID=1
......
HDL/VME64e_ActHDL/VME64xCore/VME64xCore.adf
View file @ 14081a92
......@@ -36,7 +36,7 @@ Celoxica=0
UseCeloxica=0
PHYSSYNTH_STATUS=none
RUN_MODE_SYNTH=0
SYNTH_STATUS=warnings
SYNTH_STATUS=none
IMPL_STATUS=none
PCBINTERFACE_STATUS=NONE
C_SERVER_SIM=
......@@ -168,7 +168,7 @@ MOVE_LAST_FF_STAGE=1
JOB_DESCRIPTION=JobDesc1
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log*.*:implement*.*
LAST_RUN=1273740002
LAST_RUN=1274270640
OUTPUT_NETLIST=d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL\VME64xCore\synthesis\vme64xcore_top.ngc
OUTPUT_SIMUL_NETLIST=synthesis\vme64xcore_top.vhd
Show_SliceUtilizationRatioDelta=100
......@@ -211,6 +211,7 @@ post-synthesis=1
/VME_CRCSR_test.tcl=-1
/VME_init_test.tcl=-1
/VME_top_test.tcl=-1
/WB_pipelined_test.tcl=-1
post-synthesis/..\..\synthesis\vme64xcore_top.vhd=-1
[Files.Data]
......@@ -228,5 +229,6 @@ post-synthesis/..\..\synthesis\vme64xcore_top.vhd=-1
.\src\VME_CRCSR_test.tcl=Tcl Script
.\src\VME_init_test.tcl=Tcl Script
.\src\VME_top_test.tcl=Tcl Script
.\src\WB_pipelined_test.tcl=Tcl Script
.\synthesis\vme64xcore_top.vhd=VHDL Source Code
HDL/VME64e_ActHDL/VME64xCore/VME64xCore.wsp
View file @ 14081a92
......@@ -227,55 +227,51 @@ WindowWorkspaceInfo=2C0000000000000003000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB00
[Gui config]
RunFor=100 ns
[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\WB_bus.vhd|]
CurrentLine=45
CurrentColumn=37
CurrentLine=72
CurrentColumn=45
Bookmarks=-1
BookmarksLength=3
Frame=0
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB0000005E0000009006000003030000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000012
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB83FFFF3483FFFF9089FFFFD985FFFF000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C8000000000000000000000000000000000000000900000001000000C1
[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\IRQ_controller.vhd|]
CurrentLine=29
CurrentColumn=5
CurrentLine=42
CurrentColumn=28
Bookmarks=-1
BookmarksLength=3
Frame=0
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB0000005E0000009006000003030000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000012
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB83FFFF3483FFFF9089FFFFD985FFFF000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C8000000000000000000000000000000000000000900000001000000C1
[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\VME_bus.vhd|]
CurrentLine=1201
CurrentColumn=59
CurrentLine=25
CurrentColumn=34
Bookmarks=-1
BookmarksLength=3
Frame=0
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB0000005E0000009006000003030000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000012
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB83FFFF3483FFFF9089FFFFD985FFFF000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C8000000000000000000000000000000000000000900000001000000C1
[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\VME64xCore_Top.vhd|]
CurrentLine=427
CurrentColumn=34
CurrentLine=28
CurrentColumn=105
Bookmarks=-1
BookmarksLength=3
Frame=0
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB0000005E0000009006000003030000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000012
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB83FFFF3483FFFF9089FFFFD985FFFF000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C8000000000000000000000000000000000000000900000001000000C1
[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL\VME64xCore\src\VME_top_test.tcl|]
CurrentLine=19
CurrentColumn=87
CurrentLine=126
CurrentColumn=6
Bookmarks=-1
BookmarksLength=3
Frame=0
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB0000005E0000009006000003030000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000012
[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\VME_pack.vhd|]
CurrentLine=18
CurrentColumn=122
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB83FFFF3483FFFF9089FFFFD985FFFF000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C8000000000000000000000000000000000000000900000001000000C1
[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL\VME64xCore\src\compile.do|]
CurrentLine=12
CurrentColumn=82
Bookmarks=-1
BookmarksLength=3
Frame=0
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB0000005E0000009006000003030000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000012
[CACHEDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\VME_pack.vhd|]
CurrentLine=18
CurrentColumn=122
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB83FFFF3483FFFF9089FFFFD985FFFF000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C8000000000000000000000000000000000000000900000001000000C1
[OPENDOC|Aldec.Hde.HdePlugIn.7|d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL_src\VME_pack.vhd|]
CurrentLine=20
CurrentColumn=47
Bookmarks=-1
BookmarksLength=3
Frame=0
WindowWorkspaceInfo=2C0000000000000003000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB0000005E0000009006000003030000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000014
[CACHESIMPLE|Aldec.SymbolsCommands.7]
vme64xcore=1
Built-in symbols=0
VIRTEX5=0
WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB83FFFF3483FFFF9089FFFFD985FFFF000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C8000000000000000000000000000000000000000900000001000000C1
HDL/VME64e_ActHDL/VME64xCore/compile.cfg
View file @ 14081a92
......@@ -13,8 +13,8 @@ File Time Hi=30071924
Enabled=1
State=Compiled
[file:.\..\..\VME64e_ActHDL_src\VME_bus.vhd]
File Time Lo=284683160
File Time Hi=30077558
File Time Lo=1177296936
File Time Hi=30078767
Enabled=1
State=Compiled
[file:.\src\VME_D08_test.tcl]
......@@ -43,8 +43,8 @@ File Time Hi=30066503
Enabled=1
State=Modified
[file:.\..\..\VME64e_ActHDL_src\VME_pack.vhd]
File Time Lo=-2074493802
File Time Hi=30077157
File Time Lo=1137797161
File Time Hi=30078761
Enabled=1
State=Compiled
[file:.\src\VME_init_test.tcl]
......@@ -54,27 +54,27 @@ Enabled=1
State=Modified
[file:.\src\VME_top_test.tcl]
State=Modified
File Time Lo=1956157623
File Time Hi=30071958
File Time Lo=277660624
File Time Hi=30078391
Enabled=1
[file:.\..\..\VME64e_ActHDL_src\VME64xCore_Top.vhd]
File Time Lo=-1069391231
File Time Hi=30077585
File Time Lo=-1419907683
File Time Hi=30078761
Enabled=1
State=Modified
State=Compiled
[file:.\..\..\VME64e_ActHDL_src\WB_bus.vhd]
File Time Lo=-1767308601
File Time Hi=30077593
File Time Lo=-1313887796
File Time Hi=30078767
Enabled=1
State=Modified
State=Compiled
[file:.\..\..\VME64e_ActHDL_src\IRQ_controller.vhd]
File Time Lo=-828597230
File Time Hi=30077001
File Time Lo=868158066
File Time Hi=30078760
Enabled=1
State=Compiled
[file:.\synthesis\vme64xcore_top.vhd]
File Time Lo=2020889689
File Time Hi=30071704
File Time Lo=-2137840593
File Time Hi=30078795
Enabled=1
State=Modified
LIB=vme64xcore_post_synthesis
......@@ -82,3 +82,8 @@ SIM.POST.INCLUDED=1
SIM.FUNC.INCLUDED=0
SIM.POST.AUTO=1
SIM.POST.INDEX=0
[file:.\src\WB_pipelined_test.tcl]
File Time Lo=-1320062172
File Time Hi=30078367
Enabled=1
State=Modified
HDL/VME64e_ActHDL/VME64xCore/elaboration.log
View file @ 14081a92
elbread.dll ver. 1.0.5.375 Tue May 11 10:47:00 2010
elbread.dll ver. 1.0.5.375 Mon May 17 13:49:57 2010
---------------------------------------------------------------------
......
HDL/VME64e_ActHDL_src/IRQ_controller.vhd
View file @ 14081a92
......@@ -74,6 +74,8 @@ signal VME_DS_n_oversampled : STD_LOGIC_VECTOR(1 downto 0);
signal s_reset: std_logic;
signal s_VME_IACKOUT: std_logic;
signal s_irqDTACK: std_logic; -- acknowledge of IACK cycle
signal s_applyIRQmask: std_logic; -- clears acknowlegded interrupt
signal s_IDtoData: std_logic; -- puts IRQ Status/ID register on data bus
......@@ -82,21 +84,28 @@ signal s_wbIRQrisingEdge: std_logic; -- rising edge detectio
signal s_IRQenabled: std_logic; -- indicates that interrupts are enabled (IRQlevelReg has a valid level value)
signal s_IRQreg: std_logic; -- registers pending interrupt
type t_IRQstates is (IDLE, WAIT_FOR_DS, CHECK_MATCH, APPLY_MASK_AND_DATA, PROPAGATE_IACK, APPLY_DTACK);
type t_IRQstates is ( IDLE,
WAIT_FOR_DS,
CHECK_MATCH,
APPLY_MASK_AND_DATA,
PROPAGATE_IACK,
APPLY_DTACK
);
signal s_IRQstate: t_IRQstates;
begin
s_reset <= reset_i;
irqDTACK_o <= s_irqDTACK;
irqDTACK_o <= '0' when s_irqDTACK='0' else 'Z';
VME_IACKOUT_n_o <= '0' when s_VME_IACKOUT='0' else 'Z';
p_IRQcontrolFSM: process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset='1' then
VME_IACKOUT_n_o <= 'Z';
s_irqDTACK <= 'Z';
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
......@@ -105,8 +114,8 @@ begin
case s_IRQstate is
when IDLE =>
VME_IACKOUT_n_o <= 'Z';
s_irqDTACK <= 'Z';
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
......@@ -117,8 +126,8 @@ begin
end if;
when WAIT_FOR_DS =>
VME_IACKOUT_n_o <= 'Z';
s_irqDTACK <= 'Z';
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
......@@ -129,11 +138,11 @@ begin
end if;
when CHECK_MATCH =>
VME_IACKOUT_n_o <= 'Z';
s_irqDTACK <= 'Z';
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o<= '0';
IACKinProgress_o <= '0';
if s_IACKmatch='1' then
s_IRQstate <= APPLY_MASK_AND_DATA;
else
......@@ -141,15 +150,15 @@ begin
end if;
when APPLY_MASK_AND_DATA =>
VME_IACKOUT_n_o <= 'Z';
s_irqDTACK <= 'Z';
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '1';
s_IDtoData <= '1';
IACKinProgress_o <= '1';
s_IRQstate <= APPLY_DTACK;
when APPLY_DTACK =>
VME_IACKOUT_n_o <= 'Z';
s_VME_IACKOUT <= '1';
s_irqDTACK <= '0';
s_applyIRQmask <= '0';
s_IDtoData <= '1';
......@@ -161,8 +170,8 @@ begin
end if;
when PROPAGATE_IACK =>
VME_IACKOUT_n_o <= VME_IACKIN_n_oversampled;
s_irqDTACK <= 'Z';
s_VME_IACKOUT <= VME_IACKIN_n_oversampled;
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
......@@ -173,8 +182,8 @@ begin
end if;
when OTHERS =>
VME_IACKOUT_n_o <= 'Z';
s_irqDTACK <= 'Z';
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
......@@ -203,9 +212,7 @@ begin
elsif s_applyIRQmask='1' then
s_IRQreg <= '0';
else
if s_wbIRQrisingEdge='1' and s_IRQenabled='1' then
s_IRQreg <= '1';
end if;
s_IRQreg <= s_wbIRQrisingEdge and s_IRQenabled;
end if;
end if;
end process;
......
HDL/VME64e_ActHDL_src/VME64xCore_Top.vhd
View file @ 14081a92
......@@ -172,7 +172,6 @@ component WB_bus is
ACK_i: in std_logic;
WE_o: out std_logic;
STALL_i: in std_logic;
IRQ_i: in std_logic;
memReq_i: in std_logic;
memAck_o: out std_logic;
......@@ -182,7 +181,6 @@ component WB_bus is
sel_i: in std_logic_vector(7 downto 0);
RW_i: in std_logic;
lock_i: in std_logic;
IRQ_o: out std_logic;
err_o: out std_logic;
rty_o: out std_logic;
cyc_i: in std_logic;
......@@ -192,7 +190,8 @@ component WB_bus is
FIFOrden_o: out std_logic;
FIFOwren_o: out std_logic;
FIFOdata_i: in std_logic_vector(63 downto 0);
FIFOdata_o: out std_logic_vector(63 downto 0);
FIFOdata_o: out std_logic_vector(63 downto 0);
FIFOreset_o: out std_logic;
writeFIFOempty_i: in std_logic;
TWOeInProgress_i: in std_logic;
WBbusy_o: out std_logic
......@@ -283,6 +282,8 @@ signal s_FIFOwriteEmpty: std_logic;
signal s_FIFOfull: std_logic;
signal s_FIFOwriteRden: std_logic;
signal s_FIFOreadRden: std_logic;
signal s_wbFIFOreset: std_logic;
signal s_FIFOreset: std_logic;
signal s_TWOeInProgress: std_logic;
signal s_WBbusy: std_logic;
signal s_beatCount: std_logic_vector(7 downto 0);
......@@ -297,7 +298,10 @@ begin
--CRAMdata_o <= s_CRAMdataIn;
--CRAMwea_o <= s_CRAMwea;
--CRaddr_o <= s_CRaddr;
--s_CRdata <= CRdata_i;
--s_CRdata <= CRdata_i;
s_FIFOreset <= s_wbFIFOreset or s_reset;
VME_bus_1 : VME_bus
port map(
......@@ -378,7 +382,6 @@ WB_bus_1: WB_bus
ACK_i => ACK_i,
WE_o => WE_o,
STALL_i => STALL_i,
IRQ_i => IRQ_i,
memReq_i => s_memReq,
memAck_o => s_memAckWB,
......@@ -388,7 +391,6 @@ WB_bus_1: WB_bus
sel_i => s_wbSel,
RW_i => s_RW,
lock_i => s_lock,
IRQ_o => s_IRQ,
err_o => s_err,
rty_o => s_rty,
cyc_i => s_cyc,
......@@ -398,6 +400,7 @@ WB_bus_1: WB_bus
FIFOwren_o => s_FIFOreadWren,
FIFOdata_i => s_FIFOwriteDout,
FIFOdata_o => s_FIFOreadDin,
FIFOreset_o => s_wbFIFOreset,
writeFIFOempty_i => s_FIFOwriteEmpty,
TWOeInProgress_i => s_TWOeInProgress,
WBbusy_o => s_WBbusy
......@@ -444,7 +447,7 @@ FIFO_write: FIFO
clk => clk_i,
din => s_FIFOwriteDin,
rd_en => s_FIFOwriteRden,
rst => s_reset,
rst => s_FIFOreset,
wr_en => s_FIFOwriteWren,
dout => s_FIFOwriteDout,
empty => s_FIFOwriteEmpty,
......@@ -456,7 +459,7 @@ FIFO_read: FIFO
clk => clk_i,
din => s_FIFOreadDin,
rd_en => s_FIFOreadRden,
rst => s_reset,
rst => s_FIFOreset,
wr_en => s_FIFOreadWren,
dout => s_FIFOreadDout,
empty => s_FIFOreadEmpty,
......
HDL/VME64e_ActHDL_src/VME_bus.vhd
View file @ 14081a92
This diff is collapsed.
HDL/VME64e_ActHDL_src/WB_bus.vhd
View file @ 14081a92
......@@ -44,7 +44,6 @@ entity WB_bus is
ACK_i: in std_logic;
WE_o: out std_logic;
STALL_i: in std_logic;
IRQ_i: in std_logic;
memReq_i: in std_logic;
memAck_o: out std_logic;
......@@ -54,7 +53,6 @@ entity WB_bus is
sel_i: in std_logic_vector(7 downto 0);
RW_i: in std_logic;
lock_i: in std_logic;
IRQ_o: out std_logic;
err_o: out std_logic;
rty_o: out std_logic;
cyc_i: in std_logic;
......@@ -64,7 +62,8 @@ entity WB_bus is
FIFOrden_o: out std_logic;
FIFOwren_o: out std_logic;
FIFOdata_i: in std_logic_vector(63 downto 0);
FIFOdata_o: out std_logic_vector(63 downto 0);
FIFOdata_o: out std_logic_vector(63 downto 0);
FIFOreset_o: out std_logic;
writeFIFOempty_i: in std_logic;
TWOeInProgress_i: in std_logic;
WBbusy_o: out std_logic
......@@ -98,7 +97,15 @@ signal s_ackCountEnd: std_logic; -- marks that all
signal s_FIFOrden: std_logic; -- FIFO read enable
type t_2eFSMstates is (IDLE, ADDR_LATCH, SET_CONTROL_SIGNALS, DO_PIPELINED_COMM, WAIT_FOR_END);
signal s_FIFOreset, s_FIFOreset_1, s_FIFOreset_2: std_logic; -- Resets FIFO at the end of each transfer
type t_2eFSMstates is ( IDLE,
ADDR_LATCH,
SET_CONTROL_SIGNALS,
DO_PIPELINED_COMM,
WAIT_FOR_END,
FIFO_RESET
);
signal s_2eFSMstate: t_2eFSMstates;
begin
......@@ -132,14 +139,15 @@ DAT_o <= locData_i when s_FSMactive='0' else FIFOdata_i;
ADR_o <= locAddr_i when s_FSMactive='0' else s_locAddr;
WE_o <= not RW_i when s_FSMactive='0' else s_WE;
IRQ_o <= IRQ_i;
LOCK_o <= lock_i;
err_o <= ERR_i when s_FSMactive='0' else '0';
rty_o <= RTY_i when s_FSMactive='0' else '0';
SEL_o <= sel_i when s_FSMactive='0' else (others => '1');
CYC_o <= cyc_i when s_FSMactive='0' else s_cyc;
WBbusy_o <= s_FSMactive;
WBbusy_o <= s_FSMactive;
-- 2e FSM
......@@ -153,6 +161,7 @@ begin
s_pipeCommActive <='0';
s_WE <='0';
s_addrLatch <='0';
s_FIFOreset <='0';
s_2eFSMstate <= IDLE;
else
case s_2eFSMstate is
......@@ -163,6 +172,7 @@ begin
s_WE <= not RW_i;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_FIFOreset <='0';
if TWOeInProgress_i='1' then
s_2eFSMstate <= ADDR_LATCH;
end if;
......@@ -173,6 +183,7 @@ begin
s_WE <= s_WE;
s_addrLatch <='1';
s_pipeCommActive <='0';
s_FIFOreset <='0';
s_2eFSMstate <= SET_CONTROL_SIGNALS;
when SET_CONTROL_SIGNALS =>
......@@ -180,7 +191,8 @@ begin
s_cyc <='1';
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_pipeCommActive <='0';
s_FIFOreset <='0';
s_2eFSMstate <= DO_PIPELINED_COMM;
when DO_PIPELINED_COMM =>
......@@ -189,6 +201,7 @@ begin
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='1';
s_FIFOreset <='0';
if s_ackCountEnd='1' then
s_2eFSMstate <= WAIT_FOR_END;
else
......@@ -201,16 +214,27 @@ begin
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_FIFOreset <='0';
if TWOeInProgress_i='0' then
s_2eFSMstate <= IDLE;
s_2eFSMstate <= FIFO_RESET;
end if;
when FIFO_RESET =>
s_FSMactive <='0';
s_cyc <='0';
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_FIFOreset <='1';
s_2eFSMstate <= IDLE;
when OTHERS =>
s_FSMactive <='0';
s_cyc <='0';
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_FIFOreset <='0';
s_2eFSMstate <= IDLE;
end case;
......@@ -313,7 +337,21 @@ end process;
s_FIFOrden <= '1' when s_pipeCommActive='1' and s_WE='1' and STALL_i='0' and writeFIFOempty_i='0' and s_beatCountEnd='0' else '0';
FIFOrden_o <= s_FIFOrden;
FIFOwren_o <= ACK_i when s_pipeCommActive='1' and s_WE='0' else '0';
FIFOwren_o <= ACK_i when s_pipeCommActive='1' and s_WE='0' else '0';
-- FIFO reset
p_FIFOresetStretch: process(clk_i)
begin
if rising_edge(clk_i) then
s_FIFOreset_1 <= s_FIFOreset;
s_FIFOreset_2 <= s_FIFOreset_1;
end if;
end process;
FIFOreset_o <= s_FIFOreset or s_FIFOreset_1 or s_FIFOreset_2;
......
HDL/testbenches/sim_vme64master.vhd
View file @ 14081a92
This diff is collapsed.
HDL/testbenches/sim_wbSlave.vhd
View file @ 14081a92
......@@ -33,17 +33,18 @@ entity sim_wbSlave is
DAT_i: in std_logic_vector(63 downto 0);
DAT_o: out std_logic_vector(63 downto 0);
ADR_i: in std_logic_vector(63 downto 0);
TGA_i: in std_logic_vector(3 downto 0);
TGC_i: in std_logic_vector(3 downto 0);
--TGA_i: in std_logic_vector(3 downto 0);
--TGC_i: in std_logic_vector(3 downto 0);
CYC_i: in std_logic;
ERR_o: out std_logic;
LOCK_i: in std_logic;
RTY_o: out std_logic;
SEL_i: in std_logic_vector(7 downto 0);
STB_i: in std_logic;
ACK_o: out std_logic;
ACK_o: out std_logic := '0';
WE_i: in std_logic;
IRQ_o: out std_logic_vector(6 downto 0)
STALL_o : out std_logic;
IRQ_o: out std_logic
);
end sim_wbSlave;
......@@ -55,6 +56,9 @@ signal s_ram : t_ram;
signal s_selectedData : std_logic_vector(63 downto 0);
signal s_stb_count : integer := 0;
signal s_sendCount : std_logic_vector(3 downto 0) := "0000";
begin
......@@ -62,25 +66,73 @@ begin
ERR_o <= '0';
RTY_o <= '0';
--ACK_o <= '1' when STB_i = '1';
fakeInterruot: process
begin
IRQ_o <= '0';
wait for 3500ns;
IRQ_o <= '1','0' after 50 ns;
wait;
end process;
fakeReadWrite: process
begin
if(CYC_i = '0') then wait until CYC_i = '1'; end if;
--ACK_o <= '0';
--if(CYC_i = '0') then wait until CYC_i = '1'; end if;
wait until STB_i = '1';
if STB_i /= '1' then wait until STB_i = '1'; end if;
wait until clk_i = '1';
if(WE_i = '1') then
s_ram(CONV_INTEGER(ADR_i(9 downto 0))) <= DAT_i;
report "saving data";
else
DAT_o <= s_ram(CONV_INTEGER(ADR_i(9 downto 0)));
--DAT_o <= s_ram(CONV_INTEGER(ADR_i(9 downto 0)));
end if;
wait for 10ns;
ACK_o <= '1', '0' after 10ns;
--wait for 10ns;
--ACK_o <= '1', '0' after 1ns;
end process;
DAT_o(63 downto 4) <= x"012345670123456";
DAT_o(3 downto 0) <= s_sendCount;
fakeAckReply: process
variable ack_counter : integer := 0;
begin
if(ack_counter /= s_stb_count) then
ACK_o <= '1', '0' after 1ns;
ack_counter := ack_counter +1 ;
s_sendCount <= s_sendCount +1;
end if;
wait for 30ns;
end process;
fakeSTALL: process
begin
STALL_o <= '0';
if s_stb_count = 5 then
--STALL_o <= '1','0' after 50ns; ---uncomment to test if stall works..
wait for 50ns;
end if;
wait for 1ns;
end process;
stbCounter: process(clk_i)
begin
if rising_edge(clk_i) then
if(STB_i = '1') then
s_stb_count <= s_stb_count +1;
end if;
end if;
end process;
--
end sim_wbSlave;
HDL/testbenches/vme64xcore_top_TB.vhd
View file @ 14081a92
......@@ -26,13 +26,20 @@ architecture TB_ARCHITECTURE of vme64xcore_top_tb is
VME_BBSY_n_i : in STD_LOGIC;
VME_IRQ_n_o : out STD_LOGIC_VECTOR(6 downto 0);
VME_IACKIN_n_i : in STD_LOGIC;
VME_IACKOUT_n_o : out STD_LOGIC;
VME_IACKOUT_n_o : out STD_LOGIC;
VME_DTACK_OE_o: out std_logic;
VME_DATA_DIR_o: out std_logic;
VME_DATA_OE_o: out std_logic;
VME_ADDR_DIR_o: out std_logic;
VME_ADDR_OE_o: out std_logic;
RST_i : in STD_LOGIC;
DAT_i : in STD_LOGIC_VECTOR(63 downto 0);
DAT_o : out STD_LOGIC_VECTOR(63 downto 0);
ADR_o : out STD_LOGIC_VECTOR(63 downto 0);
TGA_o : out STD_LOGIC_VECTOR(3 downto 0);
TGC_o : out STD_LOGIC_VECTOR(3 downto 0);
--TGA_o : out STD_LOGIC_VECTOR(3 downto 0);
--TGC_o : out STD_LOGIC_VECTOR(3 downto 0);
CYC_o : out STD_LOGIC;
ERR_i : in STD_LOGIC;
LOCK_o : out STD_LOGIC;
......@@ -41,26 +48,37 @@ architecture TB_ARCHITECTURE of vme64xcore_top_tb is
STB_o : out STD_LOGIC;
ACK_i : in STD_LOGIC;
WE_o : out STD_LOGIC;
IRQ_i : in STD_LOGIC_VECTOR(6 downto 0) );
STALL_i: in std_logic;
IRQ_i : in STD_LOGIC);
end component;
-- Component declaration of the "sim_vme64master(sim_vme64master)" unit defined in
-- file: "./../../testbenches/sim_vme64master.vhd"
component sim_vme64master
port(
clk_i : in STD_LOGIC;
VME_AS_n_i : out STD_LOGIC;
VME_LWORD_n_b : inout STD_LOGIC;
VME_RETRY_n_i : in STD_LOGIC;
VME_WRITE_n_o : out STD_LOGIC;
VME_DS_n_o : out STD_LOGIC_VECTOR(1 downto 0);
VME_DTACK_n_i : in STD_LOGIC;
VME_BERR_n_i : in STD_LOGIC;
VME_ADDR_b : inout STD_LOGIC_VECTOR(31 downto 1);
VME_DATA_b : inout STD_LOGIC_VECTOR(31 downto 0);
VME_AM_o : out STD_LOGIC_VECTOR(5 downto 0));
port(
clk_i : in STD_LOGIC;
VME_AS_n_i : out STD_LOGIC;
VME_LWORD_n_b : inout STD_LOGIC;
VME_RETRY_n_i : in STD_LOGIC;
VME_WRITE_n_o : out STD_LOGIC;
VME_DS_n_o : out STD_LOGIC_VECTOR(1 downto 0);
VME_DTACK_n_i : in STD_LOGIC;
VME_BERR_n_i : in STD_LOGIC;
VME_ADDR_b : inout STD_LOGIC_VECTOR(31 downto 1);
VME_DATA_b : inout STD_LOGIC_VECTOR(31 downto 0);
VME_AM_o : out STD_LOGIC_VECTOR(5 downto 0);
VME_IRQ_n_i : in STD_LOGIC_VECTOR(6 downto 0);
VME_DTACK_OE_i: in std_logic;
VME_DATA_DIR_i: in std_logic;
VME_DATA_OE_i: in std_logic;
VME_ADDR_DIR_i: in std_logic;
VME_ADDR_OE_i: in std_logic;
VME_IACKOUT_n_o : out STD_LOGIC);
end component;
for all: sim_vme64master use entity work.sim_vme64master(sim_vme64master);
-- Component declaration of the "sim_wbslave(sim_wbslave)" unit defined in
-- file: "./../../testbenches/sim_wbslave.vhd"
......@@ -71,8 +89,8 @@ architecture TB_ARCHITECTURE of vme64xcore_top_tb is
DAT_i : in STD_LOGIC_VECTOR(63 downto 0);
DAT_o : out STD_LOGIC_VECTOR(63 downto 0);
ADR_i : in STD_LOGIC_VECTOR(63 downto 0);
TGA_i : in STD_LOGIC_VECTOR(3 downto 0);
TGC_i : in STD_LOGIC_VECTOR(3 downto 0);
--TGA_i : in STD_LOGIC_VECTOR(3 downto 0);
--TGC_i : in STD_LOGIC_VECTOR(3 downto 0);
CYC_i : in STD_LOGIC;
ERR_o : out STD_LOGIC;
LOCK_i : in STD_LOGIC;
......@@ -80,8 +98,9 @@ architecture TB_ARCHITECTURE of vme64xcore_top_tb is
SEL_i : in STD_LOGIC_VECTOR(7 downto 0);
STB_i : in STD_LOGIC;
ACK_o : out STD_LOGIC;
WE_i : in STD_LOGIC;
IRQ_o : out STD_LOGIC_VECTOR(6 downto 0));
WE_i : in STD_LOGIC;
STALL_o : out STD_LOGIC;
IRQ_o : out STD_LOGIC);
end component;
for all: sim_wbslave use entity work.sim_wbslave(sim_wbslave);
......@@ -100,7 +119,8 @@ architecture TB_ARCHITECTURE of vme64xcore_top_tb is
signal ERR_i : STD_LOGIC;
signal RTY_i : STD_LOGIC;
signal ACK_i : STD_LOGIC;
signal IRQ_i : STD_LOGIC_VECTOR(6 downto 0);
signal IRQ_i : STD_LOGIC;
signal STALL_i : STD_LOGIC;
signal VME_LWORD_n_b : STD_LOGIC;
signal VME_ADDR_b : STD_LOGIC_VECTOR(31 downto 1);
signal VME_DATA_b : STD_LOGIC_VECTOR(31 downto 0);
......@@ -120,6 +140,12 @@ architecture TB_ARCHITECTURE of vme64xcore_top_tb is
signal STB_o : STD_LOGIC;
signal WE_o : STD_LOGIC;
signal VME_DTACK_OE_o:std_logic;
signal VME_DATA_DIR_o:std_logic;
signal VME_DATA_OE_o:std_logic;
signal VME_ADDR_DIR_o: std_logic;
signal VME_ADDR_OE_o:std_logic;
-- Add your code here ...
begin
......@@ -141,6 +167,13 @@ begin
VME_ADDR_b => VME_ADDR_b,
VME_DATA_b => VME_DATA_b,
VME_BBSY_n_i => VME_BBSY_n_i,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_OE_o => VME_DATA_OE_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_o => VME_ADDR_OE_o,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
......@@ -148,8 +181,8 @@ begin
DAT_i => DAT_i,
DAT_o => DAT_o,
ADR_o => ADR_o,
TGA_o => TGA_o,
TGC_o => TGC_o,
--TGA_o => TGA_o,
--TGC_o => TGC_o,
CYC_o => CYC_o,
ERR_i => ERR_i,
LOCK_o => LOCK_o,
......@@ -158,6 +191,7 @@ begin
STB_o => STB_o,
ACK_i => ACK_i,
WE_o => WE_o,
STALL_i => STALL_i,
IRQ_i => IRQ_i
);
......@@ -173,7 +207,16 @@ begin
VME_BERR_n_i => VME_BERR_n_o,
VME_ADDR_b => VME_ADDR_b,
VME_DATA_b => VME_DATA_b,
VME_AM_o => VME_AM_i
VME_AM_o => VME_AM_i,
VME_DTACK_OE_i => VME_DTACK_OE_o,
VME_DATA_DIR_i => VME_DATA_DIR_o,
VME_DATA_OE_i => VME_DATA_OE_o,
VME_ADDR_DIR_i => VME_ADDR_DIR_o,
VME_ADDR_OE_i => VME_ADDR_OE_o,
VME_IRQ_n_i => VME_IRQ_n_o,
VME_IACKOUT_n_o => VME_IACKIN_n_i
);
stimulGen_wb : sim_wbslave
......@@ -183,8 +226,8 @@ begin
DAT_i => DAT_o,
DAT_o => DAT_i,
ADR_i => ADR_o,
TGA_i => TGA_o,
TGC_i => TGC_o,
--TGA_i => TGA_o,
--TGC_i => TGC_o,
CYC_i => CYC_o,
ERR_o => ERR_i,
LOCK_i => LOCK_o,
......@@ -193,12 +236,17 @@ begin
STB_i => STB_o,
ACK_o => ACK_i,
WE_i => WE_o,
STALL_O => STALL_i,
IRQ_o => IRQ_i
);
clkGen: process
begin
clk_i<='0', '1' after 0.5 ns;
--clk_i<='0', '1' after 0.5 ns;
--wait for 0.5ns;
clk_i <= '0';
wait for 0.5ns;
clk_i <= '1';
wait for 0.5ns;
end process;
......
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