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VME64x core
Commit 0b5a72f5 authored by palvarez's avatar palvarez
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git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@86 665b4545-5c6b-4c24-801b-41150b02b44b
parent 99b46cc6
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Showing with 129 additions and 36 deletions
HDL/VFC_ISE/VME64e_VFC.gise
View file @ 0b5a72f5
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HDL/VFC_ISE/VME64e_VFC.xise
View file @ 0b5a72f5
......@@ -442,8 +442,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/vme64xcore_top_reg_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.vme64xcore_top_reg_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/vme64xcore_top_ddr3/UUT" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.VME64xCore_Top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.vme64xcore_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -467,7 +467,7 @@
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.vme64xcore_top_reg_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.VME64xCore_Top" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.vme64xcore_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
HDL/VME64e_ActHDL_src/VME_bus.vhd
View file @ 0b5a72f5
......@@ -423,15 +423,18 @@ architecture RTL of VME_bus is
signal s_latchCRdataPos : std_logic_vector(BEG_USER_CR to FUNC_ADEM);
signal s_DS1pulse_d : std_logic;
signal transfer_done_flag : std_logic;
signal s_is_d64 : std_logic;
begin
--------
s_is_d64 <= '1' when s_sel= "11111111" else '0';
--------
s_reset <= (not VME_RST_n_oversampled); -- or s_CSRarray(BIT_SET_CLR_REG)(7); -- hardware reset and software reset
reset_o <= s_reset;
-- added by pablo for testing. it was:'1' when IACKinProgress_i='1' else s_dtackOE;
VME_DATA_DIR_o <= s_dataDir; -- added by pablo for testing. it was:'1' when IACKinProgress_i='1' else s_dataDir;
VME_DATA_OE_o <= '0'; -- added by pablo for testing. it was: '1' when IACKinProgress_i='1' else s_dataOE;
VME_ADDR_DIR_o <= '0'; -- added by pablo for testing. it was:s_addrDir;
VME_ADDR_DIR_o <= s_addrDir; -- added by pablo for testing. it was:s_addrDir;
VME_ADDR_OE_o <= '0'; -- added by pablo for testing. it was:s_addrOE;
......@@ -610,7 +613,7 @@ begin
--s_dtackOE <= '0';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '0';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
......@@ -639,7 +642,7 @@ begin
--s_dtackOE <= '0';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '0';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
......@@ -665,7 +668,7 @@ begin
--s_dtackOE <= '0';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '0';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
......@@ -699,7 +702,7 @@ begin
--s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '1';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
......@@ -732,7 +735,7 @@ begin
--s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '1';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
......@@ -761,7 +764,7 @@ begin
--s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '1';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '0';
s_memReq <= '0';
......@@ -791,7 +794,7 @@ begin
--s_dtackOE <= '0';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '0';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
......@@ -826,7 +829,7 @@ begin
--s_dtackOE <= '0';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '0';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
......@@ -851,7 +854,7 @@ begin
--s_dtackOE <= '0';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '0';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
......@@ -877,7 +880,7 @@ begin
--s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '0';
s_addrDir <= VME_WRITE_n_oversampled;
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
if VME_DS_n_oversampled /= "11" then
s_mainDTACK <= '0';
......@@ -1253,7 +1256,7 @@ begin
--s_dtackOE <= '1';
s_dataDir <= '1';
s_dataOE <= '1';
s_addrDir <= '1';
s_addrDir <= s_is_d64;
s_addrOE <= '1';
s_mainDTACK <= s_mainDTACK;
s_DSlatch <= '0';
......@@ -1284,7 +1287,7 @@ begin
--s_dtackOE <= '1';
s_dataDir <= '1';
s_dataOE <= '1';
s_addrDir <= '1';
s_addrDir <= s_is_d64;
s_addrOE <= '1';
s_mainDTACK <= s_mainDTACK;
s_memReq <= '0';
......@@ -1312,7 +1315,7 @@ begin
--s_dtackOE <= '1';
s_dataDir <= '1';
s_dataOE <= '1';
s_addrDir <= '1';
s_addrDir <= s_is_d64;
s_addrOE <= '1';
-- s_mainDTACK <= not s_mainDTACK; -- s_mainDTACK;
s_mainDTACK <= s_mainDTACK;
......
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