Skip to content

V
VME64x core
Commit 08ee0223 authored by dpedrett's avatar dpedrett
Browse files
Options

stall signal added 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@140 665b4545-5c6b-4c24-801b-41150b02b44b
parent e9346a64
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 198 additions and 180 deletions
hdl/boards/vfc/rtl/TOP_LEVEL.vhd
View file @ 08ee0223
......@@ -298,7 +298,7 @@ Rst <= VME_RST_n_i and Reset;
-- CLKIN_PERIOD => 50.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- -- MHz).
-- -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
-- CLKOUT0_DIVIDE => 30,
-- CLKOUT0_DIVIDE => 12,
-- CLKOUT1_DIVIDE => 1,
-- CLKOUT2_DIVIDE => 1,
-- CLKOUT3_DIVIDE => 1,
......
hdl/boards/vfc/rtl/xwb_dpram.vhd
View file @ 08ee0223
......@@ -98,6 +98,7 @@ signal s_Int_Count_o : std_logic_vector(31 downto 0);
signal s_Int_Count_o1 : std_logic_vector(31 downto 0);
signal s_Read_IntCount : std_logic;
signal s_rst : std_logic;
signal s_stall : std_logic;
begin
s_rst <= not(rst_n_i);
s_q_o1 <= s_INT_COUNT & s_FREQ;
......@@ -183,7 +184,7 @@ Inst_IRQ_generator: IRQ_generator PORT MAP(
s_bwea <= slave1_i.sel when s_wea = '1' else f_zeros(c_wishbone_data_width/8); --it was slave1_in.sel
-- s_bweb <= slave2_in.sel when s_web = '1' else f_zeros(c_wishbone_data_width/8);
s_wea <= slave1_i.we and slave1_i.cyc and slave1_i.stb; -- it was slave1_in.we and slave1_in.stb and slave1_in.cyc;
s_wea <= slave1_i.we and slave1_i.cyc and slave1_i.stb and (not s_stall); -- it was slave1_in.we and slave1_in.stb and slave1_in.cyc;
--s_web <= slave2_in.we and slave2_in.stb and slave2_in.cyc;
process(clk_sys_i)
......@@ -196,7 +197,7 @@ Inst_IRQ_generator: IRQ_generator PORT MAP(
if(slave1_out.ack = '1' and g_slave1_interface_mode = CLASSIC) then
slave1_out.ack <= '0';
else
slave1_out.ack <= slave1_i.cyc and slave1_i.stb;
slave1_out.ack <= slave1_i.cyc and slave1_i.stb and (not s_stall) ;
end if;
-- if(slave2_out.ack = '1' and g_slave2_interface_mode = CLASSIC) then
......@@ -207,9 +208,19 @@ Inst_IRQ_generator: IRQ_generator PORT MAP(
end if;
end if;
end process;
process(clk_sys_i)
begin
if(rising_edge(clk_sys_i)) then
if(s_rst = '0') or slave1_out.ack = '1' then
s_stall <= '1';
elsif slave1_i.cyc = '1' then
s_stall <= '0';
end if;
end if;
end process;
slave1_o.dat <= s_q_o1 when unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0)) = 0 else s_q_o;
slave1_o.stall <= '0';
slave1_o.stall <= s_stall;
-- slave2_out.stall <= '0';
slave1_o.err <= '0';
--slave2_out.err <= '0';
......
hdl/boards/vfc/syn/VME64xTest.xise
View file @ 08ee0223
......@@ -122,6 +122,10 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/vme64x_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 08ee0223
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment