Commit 05081240 authored by Tristan Gingold's avatar Tristan Gingold

Add README, adjust

parent dc69f930
VME64x Core
Running the testbench
After having cloned the repository, simply do:
git submodule init
git submodule update
cd hdl/testbench/simple_tb/modelsim
This is an automatic testbench with a yes/no status.
It runs the testbench several times with a different scenario value.
The last line should be: OK!
Tested with ModelSim SE-64 10.2a on linux.
......@@ -3,6 +3,5 @@ files = [
modules = {
"local": [ "../../rtl" ],
"git": "git://",
"local": [ "../../rtl", "../../ip_cores/general-cores" ],
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