hdl/rtl/xvme64x_core.vhd | hdl/rtl/vme64x_core_verilog.vhd add default return for functions

02a397d1 · Sebastian Owarzany · fbd7dbbf · 02a397d1 · 02a397d1
Commit 02a397d1 authored Dec 20, 2022 by Sebastian Owarzany
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Showing with 6 additions and 3 deletions

vme64x_core_verilog.vhd hdl/rtl/vme64x_core_verilog.vhd +4 -1

xvme64x_core.vhd hdl/rtl/xvme64x_core.vhd +2 -2

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--- a/hdl/rtl/vme64x_core_verilog.vhd
+++ b/hdl/rtl/vme64x_core_verilog.vhd
@@ -131,7 +131,9 @@ entity vme64x_core_verilog is
    if X = "BYTE" then
      return BYTE ;
    end if;
+	  return BYTE ;
  end string_to_wb_grn ;
+
 function string_to_wb_mode(X : string)
              return t_wishbone_interface_mode is
  begin
@@ -141,6 +143,7 @@ entity vme64x_core_verilog is
    if X = "PIPELINED" then
      return PIPELINED ;
    end if;
+	  return PIPELINED ;
  end string_to_wb_mode ;

 end vme64x_core_verilog;

--- a/hdl/rtl/xvme64x_core.vhd
+++ b/hdl/rtl/xvme64x_core.vhd
@@ -120,7 +120,6 @@ entity xvme64x_core is
    g_END_SN          : std_logic_vector(23 downto 0)  := x"000000";

    g_USE_CUSTOM_ADER : Boolean := false;
-    
    -- Function decoder parameters.
    g_DECODER         : t_vme64x_decoder_arr := c_vme64x_decoders_default);
  port (
@@ -192,6 +191,7 @@ architecture rtl of xvme64x_core is
            return i;
        end if;
    end loop;
+    return 0;
  end least_set_bit;

  -- Compute the ADER for each function if CR/CSR is not used. For example: