Commit fbd7dbbf authored by Sebastian Owarzany's avatar Sebastian Owarzany

hdl/sim/vme64x_bfm/components/sn74vmeh22501.v add explicitly netttypes

parent 42f6c768
`timescale 1ns/1ns
`timescale 1ns/1ns
module sn74vmeh22501 (
input oeab1,
oeby1_n,
a1,
output y1,
inout b1,
input oeab2,
oeby2_n,
a2,
output y2,
inout b2,
input oe_n,
input dir,
clkab,
le,
clkba,
inout [1:8] a3,
inout [1:8] b3);
input wire oeab1,
wire oeby1_n,
wire a1,
output wire y1,
inout wire b1,
input wire oeab2,
wire oeby2_n,
wire a2,
output wire y2,
inout wire b2,
input wire oe_n,
input wire dir,
wire clkab,
wire le,
wire clkba,
inout wire [1:8] a3,
inout wire [1:8] b3);
assign b1 = oeab1 ? a1 : 1'bz;
assign y1 = oeby1_n ? 1'bz : b1;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment