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VME64x core
Commit 0063029a authored by rstefanic's avatar rstefanic
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git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@18 665b4545-5c6b-4c24-801b-41150b02b44b
parent 64ba6840
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HDL/VME64e_ActHDL/VME64xCore/VME64xCore.LIB
View file @ 0063029a
timestamp=1268665547382
timestamp=1273754497258
[~A]
ModifyID=1
......
HDL/VME64e_ActHDL/VME64xCore/VME64xCore.adf
View file @ 0063029a
......@@ -36,7 +36,7 @@ Celoxica=0
UseCeloxica=0
PHYSSYNTH_STATUS=none
RUN_MODE_SYNTH=0
SYNTH_STATUS=errors
SYNTH_STATUS=warnings
IMPL_STATUS=none
PCBINTERFACE_STATUS=NONE
C_SERVER_SIM=
......@@ -44,6 +44,7 @@ C_SERVER_SYNTH=
C_SERVER_IMPL=
VerilogDirsChanged=0
FUNC_LIB=vme64xcore
TIM_LIB=vme64xcore_timing
POST_LIB=vme64xcore_post_synthesis
[IMPLEMENTATION]
......@@ -53,14 +54,14 @@ FLOW_STEPS_RESET=0
FAMILY=Xilinx10x VIRTEX5
DEVICE=5vlx20tff323
SPEED=-2
NETLIST=D:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL\VME64xCore\synthesis\vme_bus.ngc
NETLIST=d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL\VME64xCore\synthesis\vme64xcore_top.ngc
[PHYS_SYNTHESIS]
FAMILY=Xilinx10x VIRTEX5
DEVICE=5vlx20tff323
SPEED=-2
SCRIPTS_COPIED=0
IN_DESIGN=D:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL\VME64xCore\synthesis\vme_bus.ngc
IN_DESIGN=d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL\VME64xCore\synthesis\vme64xcore_top.ngc
OUT_DESIGN=
IN_CONSTRAINT=
OUT_CONSTRAINT=
......@@ -73,7 +74,8 @@ impl_opt(dont_run_place)=0
impl_opt(dont_run_trace)=0
impl_opt(dont_run_simulation)=0
impl_opt(dont_run_fit)=0
impl_opt(dont_run_bitgen)=1
impl_opt(dont_run_bitgen)=0
impl_opt(Macro_Search_Path)=D:/CSL/SVN/FAIR-VME64ext/trunk/HDL/IP_cores
[PCB_INTERFACE]
FAMILY=
......@@ -83,7 +85,7 @@ FAMILY=Xilinx10x VIRTEX5
DEVICE=5vlx20tff323
SPEED=-2
OBSOLETE_ALIASES=1
TOPLEVEL=vme_bus
TOPLEVEL=vme64xcore_top
FILTER_MESSAGES=
FSM_ENCODE=
PACK_IO_REGISTERS=Auto
......@@ -166,33 +168,65 @@ MOVE_LAST_FF_STAGE=1
JOB_DESCRIPTION=JobDesc1
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log*.*:implement*.*
LAST_RUN=1268325404
OUTPUT_NETLIST=D:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL\VME64xCore\synthesis\vme_bus.ngc
OUTPUT_SIMUL_NETLIST=D:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL\VME64xCore\synthesis\vme_bus.vhd
LAST_RUN=1273740002
OUTPUT_NETLIST=d:\CSL\SVN\FAIR-VME64ext\trunk\HDL\VME64e_ActHDL\VME64xCore\synthesis\vme64xcore_top.ngc
OUTPUT_SIMUL_NETLIST=synthesis\vme64xcore_top.vhd
Show_SliceUtilizationRatioDelta=100
Show_MultiplierStyle=Auto
Show_MaxNoBufgs24=24
Show_MaxNoBufgs16=16
Show_ConvertTristatesToLogic=Yes
Show_MaxNoBufgs4=4
Show_MultiplierStyle2=LUT
Show_UseDSP48=Auto
Show_NumberOfRegionalClockBuffers=16
[HierarchyViewer]
SortInfo=u
HierarchyInformation=vme_bus|rtl|0
HierarchyInformation=
ShowHide=ShowTopLevel
Selected=
[file_out:/VME64xCore_Top.bde]
/..\compile\VME64xCore_Top.vhd=-1
[file_out:/..\..\..\VME64e_ActHDL_src\VME64xCore_Top.bde]
/..\compile\VME64xCore_Top.vhd=-1
[Groups]
post-synthesis=1
[Files]
/compile.do=-1
/..\..\..\VME64e_ActHDL_src\VME_pack.vhd=-1
/..\..\..\VME64e_ActHDL_src\SharedComps.vhd=-1
/..\..\..\VME64e_ActHDL_src\VME_bus.vhd=-1
/..\..\..\VME64e_ActHDL_src\WB_bus.vhd=-1
/..\..\..\VME64e_ActHDL_src\IRQ_controller.vhd=-1
/..\..\..\VME64e_ActHDL_src\VME64xCore_Top.vhd=-1
/compile.do=-1
/VME_D08_test.tcl=-1
/VME_D16_test.tcl=-1
/VME_D64_test.tcl=-1
/VME_unaligned_test.tcl=-1
/VME_CRCSR_test.tcl=-1
/VME_init_test.tcl=-1
/VME_top_test.tcl=-1
post-synthesis/..\..\synthesis\vme64xcore_top.vhd=-1
[Files.Data]
.\src\compile.do=Macro
.\..\..\VME64e_ActHDL_src\VME_pack.vhd=VHDL Source Code
.\..\..\VME64e_ActHDL_src\SharedComps.vhd=VHDL Source Code
.\..\..\VME64e_ActHDL_src\VME_bus.vhd=VHDL Source Code
.\..\..\VME64e_ActHDL_src\WB_bus.vhd=VHDL Source Code
.\..\..\VME64e_ActHDL_src\IRQ_controller.vhd=VHDL Source Code
.\..\..\VME64e_ActHDL_src\VME64xCore_Top.vhd=VHDL Source Code
.\src\compile.do=Macro
.\src\VME_D08_test.tcl=Tcl Script
.\src\VME_D16_test.tcl=Tcl Script
.\src\VME_D64_test.tcl=Tcl Script
.\src\VME_unaligned_test.tcl=Tcl Script
.\src\VME_CRCSR_test.tcl=Tcl Script
.\src\VME_init_test.tcl=Tcl Script
.\src\VME_top_test.tcl=Tcl Script
.\synthesis\vme64xcore_top.vhd=VHDL Source Code
HDL/VME64e_ActHDL/VME64xCore/VME64xCore.wsp
View file @ 0063029a
This diff is collapsed.
HDL/VME64e_ActHDL/VME64xCore/compilation.order
View file @ 0063029a
.\..\..\VME64e_ActHDL_src\VME_pack.vhd
.\..\..\VME64e_ActHDL_src\SharedComps.vhd
.\..\..\VME64e_ActHDL_src\VME_bus.vhd
.\..\..\VME64e_ActHDL_src\WB_bus.vhd
.\..\..\VME64e_ActHDL_src\IRQ_controller.vhd
.\..\..\VME64e_ActHDL_src\VME64xCore_Top.vhd
.\synthesis\vme64xcore_top.vhd
HDL/VME64e_ActHDL/VME64xCore/compile.cfg
View file @ 0063029a
......@@ -3,37 +3,82 @@ Entity=
Architecture=
TopLevelType=
[file:.\src\compile.do]
File Time Lo=1934454697
File Time Hi=30065141
File Time Lo=594028693
File Time Hi=30070530
Enabled=1
State=Modified
[file:.\..\..\VME64e_ActHDL_src\SharedComps.vhd]
File Time Lo=649984398
File Time Hi=30065141
File Time Lo=-710240302
File Time Hi=30071924
Enabled=1
State=Compiled
[file:.\..\..\VME64e_ActHDL_src\VME_bus.vhd]
File Time Lo=-2142650858
File Time Hi=30065744
File Time Lo=284683160
File Time Hi=30077558
Enabled=1
State=Compiled
[file:.\src\VME_D08_test.tcl]
State=Modified
File Time Lo=-2045890397
File Time Hi=30065734
File Time Lo=-1938167069
File Time Hi=30066487
Enabled=1
[file:.\src\VME_D16_test.tcl]
File Time Lo=-1453129471
File Time Hi=30065735
File Time Lo=-148907505
File Time Hi=30066137
Enabled=1
State=Modified
[file:.\src\VME_D64_test.tcl]
File Time Lo=411431569
File Time Hi=30065737
File Time Lo=173233061
File Time Hi=30066138
Enabled=1
State=Modified
[file:.\src\VME_unaligned_test.tcl]
File Time Lo=614849880
File Time Hi=30065740
File Time Lo=671809937
File Time Hi=30066138
Enabled=1
State=Modified
[file:.\src\VME_CRCSR_test.tcl]
File Time Lo=-1272663866
File Time Hi=30066503
Enabled=1
State=Modified
[file:.\..\..\VME64e_ActHDL_src\VME_pack.vhd]
File Time Lo=-2074493802
File Time Hi=30077157
Enabled=1
State=Compiled
[file:.\src\VME_init_test.tcl]
File Time Lo=1631506631
File Time Hi=30067747
Enabled=1
State=Modified
[file:.\src\VME_top_test.tcl]
State=Modified
File Time Lo=1956157623
File Time Hi=30071958
Enabled=1
[file:.\..\..\VME64e_ActHDL_src\VME64xCore_Top.vhd]
File Time Lo=-1069391231
File Time Hi=30077585
Enabled=1
State=Modified
[file:.\..\..\VME64e_ActHDL_src\WB_bus.vhd]
File Time Lo=-1767308601
File Time Hi=30077593
Enabled=1
State=Modified
[file:.\..\..\VME64e_ActHDL_src\IRQ_controller.vhd]
File Time Lo=-828597230
File Time Hi=30077001
Enabled=1
State=Compiled
[file:.\synthesis\vme64xcore_top.vhd]
File Time Lo=2020889689
File Time Hi=30071704
Enabled=1
State=Modified
LIB=vme64xcore_post_synthesis
SIM.POST.INCLUDED=1
SIM.FUNC.INCLUDED=0
SIM.POST.AUTO=1
SIM.POST.INDEX=0
HDL/VME64e_ActHDL/VME64xCore/elaboration.log
View file @ 0063029a
elbread.dll ver. 1.0.5.375 Mon Mar 15 16:05:37 2010
elbread.dll ver. 1.0.5.375 Tue May 11 10:47:00 2010
------------------------------------------------------------------
Entity | Architecture | Library
------------------------------------------------------------------
---------------------------------------------------------------------
Entity | Architecture | Library
---------------------------------------------------------------------
vme64xcore_top | rtl | vme64xcore
vme_bus | rtl | vme64xcore
wb_bus | rtl | vme64xcore
irq_controller | rtl | vme64xcore
cr | cr_a | vme64xcore
cram | cram_a | vme64xcore
fifo | fifo_a | vme64xcore
risedgedetection | rtl | vme64xcore
siginputsampleandfallingedgedetection | rtl | vme64xcore
siginputsampleandrisingedgedetection | rtl | vme64xcore
siginputsampleandedgedetection | rtl | vme64xcore
reginputsample | rtl | vme64xcore
siginputsample | rtl | vme64xcore
------------------------------------------------------------------
blk_mem_gen_v3_1 | behavioral | xilinxcorelib
blk_mem_gen_v3_1_output_stage | behavioral | xilinxcorelib
fifo_generator_v5_1 | behavioral | xilinxcorelib
fifo_generator_v5_1_bhv_ss | behavioral | xilinxcorelib
fifo_generator_v5_1_bhv_as | behavioral | xilinxcorelib
fifo_generator_v5_1_bhv_preload0 | behavioral | xilinxcorelib
---------------------------------------------------------------------
-----------------------------
Package | Library
-----------------------------
--------------------------------
Package | Library
--------------------------------
standard | std
textio | std
std_logic_1164 | ieee
std_logic_arith | ieee
vme_pack | vme64xcore
std_logic_unsigned | ieee
-----------------------------
std_logic_textio | ieee
--------------------------------
HDL/VME64e_ActHDL/VME64xCore/src/VME_top_test.tcl
View file @ 0063029a
......@@ -48,7 +48,7 @@ wave VME_bus_1/s_FUNC_AM(0)
wave s_memReq
wave s_memAckWB
wave VME_bus_1/s_memAckCSR
wave VME_bus_1/s_memAckCSR(2)
wave VME_bus_1/s_CSRaddressed
wave VME_bus_1/s_CRAMaddressed
wave VME_bus_1/s_CRaddressed
......@@ -96,7 +96,7 @@ wave ADR_o
force clk_i 0 0, 1 0.5 ns -r 1 ns
force VME_RST_n_i 1 0
force VME_RST_n_i 0 0, 1 2 ns
force VME_AS_n_i 1 0, 0 110 ns, 1 165 ns, 0 180 ns, 1 198 ns, 0 200 ns, 1 211 ns, 0 225 ns, 1 275 ns, 0 285 ns, 1 310 ns, 0 320 ns, 1 345 ns, 0 365 ns, 1 380 ns, 0 425 ns, 1 435 ns, 0 445 ns, 1 455 ns, 0 470 ns, 1 520 ns, 0 530 ns
force VME_DS_n_i "11" 0, "10" 120 ns, "11" 135 ns, "10" 145 ns, "11" 160 ns, "10" 181 ns, "11" 192 ns, "10" 201 ns, "11" 210 ns, "00" 226 ns, "11" 270 ns, "10" 290 ns, "11" 305 ns, "10" 325 ns, "11" 454 ns, "10" 472 ns, "11" 481 ns, "10" 488 ns, "00" 496 ns, "10" 504 ns, "00" 512 ns, "11" 518 ns, "10" 532 ns, "11" 541 ns, "10" 548 ns, "00" 556 ns
......@@ -108,9 +108,9 @@ force VME_WRITE_n_i 1 0, 0 144 ns, 1 220 ns, 0 280 ns, 1 315 ns, 0 496 ns, 1 529
force VME_BBSY_n_i 1 1, 0 420 ns, 1 460 ns
force VME_DATA_b "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" 0, "16#10" 144 ns, "16#FF" 169 ns, "16#05" 200 ns, "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" 220 ns, "16#AB" 280 ns, "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" 315 ns, "16#00000000" 469 ns, "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" 553 ns
force VME_DATA_b "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" 0, "16#10" 144 ns, "16#FF" 169 ns, "16#49" 200 ns, "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" 220 ns, "16#AB" 280 ns, "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" 315 ns, "16#00000000" 469 ns, "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" 553 ns
#"16#34"
#"16#49"
#"16#05"
force VME_GA_i "011111" 0
#force s_WBdataOut "16#FFFFFFFF" 0
......
HDL/VME64e_ActHDL/VME64xCore/synthesis.order
View file @ 0063029a
i<>.\..\..\VME64e_ActHDL_src\VME_pack.vhd
i<>.\..\..\VME64e_ActHDL_src\SharedComps.vhd
i<>.\..\..\VME64e_ActHDL_src\VME_bus.vhd
i<>.\..\..\VME64e_ActHDL_src\VME64xCore_Top.vhd
i<>.\..\..\VME64e_ActHDL_src\WB_bus.vhd
i<>.\..\..\VME64e_ActHDL_src\IRQ_controller.vhd
HDL/VME64e_ActHDL_src/IRQ_controller.vhd
View file @ 0063029a
......@@ -23,7 +23,8 @@
--{entity {IRQ_controller} architecture {RTL}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity IRQ_controller is
port(
......@@ -36,15 +37,16 @@ entity IRQ_controller is
VME_DS_n_i : in STD_LOGIC_VECTOR(1 downto 0);
irqDTACK_o : out std_logic;
IACKinProgress_o: out std_logic;
IRQ_i: in std_logic_vector(6 downto 0);
IRQ_i: in std_logic;
locAddr_i: in std_logic_vector(3 downto 1);
IDtoData_o: out std_logic
IDtoData_o: out std_logic;
IRQlevelReg_i: in std_logic_vector(7 downto 0)
);
end IRQ_controller;
architecture RTL of IRQ_controller is
component StretchedRisEdgeDetection is
component RisEdgeDetection is
port (
sig_i, clk_i: in std_logic;
RisEdge_o: out std_logic );
......@@ -72,13 +74,13 @@ signal VME_DS_n_oversampled : STD_LOGIC_VECTOR(1 downto 0);
signal s_reset: std_logic;
signal s_IRQreg: std_logic_vector(6 downto 0); -- stores information on pending interrupt requests
signal s_irqDTACK: std_logic; -- acknowledge of IACK cycle
signal s_applyIRQmask: std_logic; -- used for clearing acknowledged interrupt requests
signal s_irqDTACK: std_logic; -- acknowledge of IACK cycle
signal s_applyIRQmask: std_logic; -- clears acknowlegded interrupt
signal s_IDtoData: std_logic; -- puts IRQ Status/ID register on data bus
signal s_IACKmatch: std_logic; -- signals that an active interrupt is being acknowledged
signal s_IRQclearMask: std_logic_vector(6 downto 0); -- mask for clearing acknowledged interrupts
signal s_wbIRQrisingEdge: std_logic_vector(6 downto 0); -- rising edge detection on interrupt lines
signal s_wbIRQrisingEdge: std_logic; -- rising edge detection on interrupt line
signal s_IRQenabled: std_logic; -- indicates that interrupts are enabled (IRQlevelReg has a valid level value)
signal s_IRQreg: std_logic; -- registers pending interrupt
type t_IRQstates is (IDLE, WAIT_FOR_DS, CHECK_MATCH, APPLY_MASK_AND_DATA, PROPAGATE_IACK, APPLY_DTACK);
signal s_IRQstate: t_IRQstates;
......@@ -182,17 +184,10 @@ begin
end if;
end if;
end process;
s_IRQclearMask <= "0000001" when locAddr_i="001" else
"0000010" when locAddr_i="010" else
"0000100" when locAddr_i="011" else
"0001000" when locAddr_i="100" else
"0010000" when locAddr_i="101" else
"0100000" when locAddr_i="110" else
"1000000" when locAddr_i="111" else
"0000000";
s_IACKmatch <= '1' when (s_IRQclearMask and s_IRQreg)/="0000000" else '0';
s_IACKmatch <= '1' when "00000"&locAddr_i = IRQlevelReg_i else '0';
s_IRQenabled <= '1' when IRQlevelReg_i < 8 and IRQlevelReg_i /= 0 else '0';
IDtoData_o <= s_IDtoData;
......@@ -200,36 +195,27 @@ p_IRQregHandling: process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset='1' then
s_IRQreg <= (others => '0');
s_IRQreg <= '0';
elsif s_applyIRQmask='1' then
for i in 0 to 6 loop
if s_IRQclearMask(i)='1' then
s_IRQreg(i) <= '0';
end if;
end loop;
s_IRQreg <= '0';
else
for i in 0 to 6 loop
if s_wbIRQrisingEdge(i)='1' then -- s_wbIRQrisingEdge is 2 clock cycles long so an interrupt wouldn't be missed because of s_applyIRQmask priority
s_IRQreg(i) <= '1';
end if;
end loop;
if s_wbIRQrisingEdge='1' and s_IRQenabled='1' then
s_IRQreg <= '1';
end if;
end if;
end if;
end process;
gen2: for i in 0 to 6 generate
VME_IRQ_n_o(i) <= '0' when s_IRQreg(i)='1' else 'Z';
end generate;
gen_IRQoutput: for i in 0 to 6 generate
VME_IRQ_n_o(i) <= '0' when s_IRQreg='1' and IRQlevelReg_i=(i+1) else 'Z';
end generate;
gen1: for i in 0 to 6 generate
IRQrisingEdge: StretchedRisEdgeDetection
IRQrisingEdge: RisEdgeDetection
port map (
sig_i => IRQ_i(i),
sig_i => IRQ_i,
clk_i => clk_i,
RisEdge_o => s_wbIRQrisingEdge(i)
RisEdge_o => s_wbIRQrisingEdge
);
end generate;
IACKINinputSample: SigInputSample
port map(
......
HDL/VME64e_ActHDL_src/VME64xCore_Top.vhd
View file @ 0063029a
This diff is collapsed.
HDL/VME64e_ActHDL_src/VME_bus.vhd
View file @ 0063029a
This diff is collapsed.
HDL/VME64e_ActHDL_src/VME_pack.vhd
View file @ 0063029a
......@@ -39,13 +39,8 @@ package VME_pack is
constant FUNC0_ADER_1 : integer := 33;
constant FUNC0_ADER_2 : integer := 34;
constant FUNC0_ADER_3 : integer := 35;
constant IRQ_ID_7 : integer := 36;
constant IRQ_ID_6 : integer := 37;
constant IRQ_ID_5 : integer := 38;
constant IRQ_ID_4 : integer := 39;
constant IRQ_ID_3 : integer := 40;
constant IRQ_ID_2 : integer := 41;
constant IRQ_ID_1 : integer := 42;
constant IRQ_ID : integer := 36;
constant IRQ_level : integer := 37;
constant BAR_addr : std_logic_vector(18 downto 0) := "1111111111111111111";
constant BIT_SET_REG_addr : std_logic_vector(18 downto 0) := "1111111111111111011";
......@@ -85,13 +80,8 @@ package VME_pack is
constant FUNC0_ADER_1_addr : std_logic_vector(18 downto 0) := "1111111111101101011";
constant FUNC0_ADER_2_addr : std_logic_vector(18 downto 0) := "1111111111101100111";
constant FUNC0_ADER_3_addr : std_logic_vector(18 downto 0) := "1111111111101100011";
constant IRQ_ID_7_addr : std_logic_vector(18 downto 0) := "1111111101111111111";
constant IRQ_ID_6_addr : std_logic_vector(18 downto 0) := "1111111101111111011";
constant IRQ_ID_5_addr : std_logic_vector(18 downto 0) := "1111111101111110111";
constant IRQ_ID_4_addr : std_logic_vector(18 downto 0) := "1111111101111110011";
constant IRQ_ID_3_addr : std_logic_vector(18 downto 0) := "1111111101111101111";
constant IRQ_ID_2_addr : std_logic_vector(18 downto 0) := "1111111101111101011";
constant IRQ_ID_1_addr : std_logic_vector(18 downto 0) := "1111111101111100111";
constant IRQ_ID_addr : std_logic_vector(18 downto 0) := "1111111101111111111";
constant IRQ_level_addr : std_logic_vector(18 downto 0) := "1111111101111111011";
constant BEG_USER_CR_0: integer := 1;
......@@ -145,7 +135,7 @@ package VME_pack is
constant FUNC7_ADEM_2 : integer := 49;
constant FUNC7_ADEM_3 : integer := 50;
type t_reg36x8bit is array(42 downto 0) of std_logic_vector(7 downto 0);
type t_reg38x8bit is array(37 downto 0) of std_logic_vector(7 downto 0);
type t_reg52x8bit is array(51 downto 0) of std_logic_vector(7 downto 0);
type t_reg52x12bit is array(51 downto 0) of std_logic_vector(11 downto 0);
......
HDL/VME64e_ActHDL_src/WB_bus.vhd
View file @ 0063029a
......@@ -43,7 +43,8 @@ entity WB_bus is
STB_o: out std_logic;
ACK_i: in std_logic;
WE_o: out std_logic;
IRQ_i: in std_logic_vector(6 downto 0);
STALL_i: in std_logic;
IRQ_i: in std_logic;
memReq_i: in std_logic;
memAck_o: out std_logic;
......@@ -53,17 +54,20 @@ entity WB_bus is
sel_i: in std_logic_vector(7 downto 0);
RW_i: in std_logic;
lock_i: in std_logic;
IRQ_o: out std_logic_vector(6 downto 0);
IRQ_o: out std_logic;
err_o: out std_logic;
rty_o: out std_logic;
cyc_i: in std_logic;
mainFSMreset_i: in std_logic;
beatCount_i: in std_logic_vector(7 downto 0);
FIFOrden_o: out std_logic;
FIFOwren_o: out std_logic;
FIFOdata_i: in std_logic_vector(63 downto 0);
FIFOempty_i: in std_logic;
SSTinProgress_i: in std_logic;
FIFOdata_o: out std_logic_vector(63 downto 0);
writeFIFOempty_i: in std_logic;
TWOeInProgress_i: in std_logic;
WBbusy_o: out std_logic
);
......@@ -79,11 +83,16 @@ SIgnal s_locAddr: std_logic_vector(63 downto 0); -- local address
signal s_FSMactive: std_logic; -- signals when SST FIFO is being emptied
signal s_cyc: std_logic;
signal s_stb: std_logic;
signal s_addrIncrement: std_logic; -- increment address for block transfers
signal s_addrLatch: std_logic; -- store initial address locally
signal s_addrLatch: std_logic; -- store initial address locally
type t_sstFSMstates is (IDLE, ADDR_LATCH, FIFO_CHECK, RDEN_SET, STB_SET, ADDR_INCREMENT, RETRY, CYC_ON);
signal s_sstFSMstate: t_sstFSMstates;
signal s_pipeCommActive: std_logic;
signal s_WE: std_logic;
signal s_runningBeatCount: std_logic_vector(8 downto 0);
type t_2eFSMstates is (IDLE, ADDR_LATCH, FIFO_CHECK, RDEN_SET, STB_SET, ADDR_INCREMENT, RETRY, CYC_ON);
signal s_2eFSMstate: t_2eFSMstates;
begin
......@@ -114,7 +123,7 @@ DAT_o <= locData_i when s_FSMactive='0' else FIFOdata_i;
ADR_o <= locAddr_i when s_FSMactive='0' else s_locAddr;
WE_o <= not RW_i when s_FSMactive='0' else '1';
WE_o <= not RW_i when s_FSMactive='0' else s_WE;
IRQ_o <= IRQ_i;
LOCK_o <= lock_i;
err_o <= ERR_i when s_FSMactive='0' else '0';
......@@ -133,104 +142,54 @@ begin
if s_reset='1' then
s_FSMactive <='0';
s_cyc <='0';
s_stb <='0';
FIFOrden_o <='0';
s_addrIncrement <='0';
s_pipeCommActive <='0';
s_WE <='0';
s_addrLatch <='0';
s_sstFSMstate <= IDLE;
s_2eFSMstate <= IDLE;
else
case s_sstFSMstate is
case s_2eFSMstate is
when IDLE =>
s_FSMactive <='0';
s_cyc <='0';
s_stb <='0';
FIFOrden_o <='0';
s_addrIncrement <='0';
s_WE <= not RW_i;
s_addrLatch <='0';
if SSTinProgress_i='1' then
s_sstFSMstate <= ADDR_LATCH;
s_pipeCommActive <='0';
if TWOeInProgress_i='1' then
s_2eFSMstate <= ADDR_LATCH;
end if;
when ADDR_LATCH =>
s_FSMactive <='1';
s_cyc <='0';
s_stb <='0';
FIFOrden_o <='0';
s_addrIncrement <='0';
s_WE <= s_WE;
s_addrLatch <='1';
s_sstFSMstate <= FIFO_CHECK;
when FIFO_CHECK =>
s_FSMactive <='1';
s_cyc <='1';
s_stb <='0';
FIFOrden_o <='0';
s_addrIncrement <='0';
s_addrLatch <='0';
if FIFOempty_i='0' then
s_sstFSMstate <= RDEN_SET;
elsif SSTinProgress_i='0' then
s_sstFSMstate <= IDLE;
end if;
when RDEN_SET =>
s_FSMactive <='1';
s_cyc <='1';
s_stb <='0';
FIFOrden_o <='1';
s_addrIncrement <='0';
s_addrLatch <='0';
s_sstFSMstate <= STB_SET;
when STB_SET =>
s_pipeCommActive <='0';
s_2eFSMstate <= SET_CONTROL_SIGNALS;
when SET_CONTROL_SIGNALS =>
s_FSMactive <='1';
s_cyc <='1';
s_stb <='1';
FIFOrden_o <='0';
s_addrIncrement <='0';
s_addrLatch <='0';
if ACK_i='1' then
s_sstFSMstate <= ADDR_INCREMENT;
elsif RTY_i='1' or ERR_i='1' then
s_sstFSMstate <= RETRY;
end if;
when ADDR_INCREMENT =>
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_2eFSMstate <= DO_PIPELINED_COMM;
when DO_PIPELINED_COMM =>
s_FSMactive <='1';
s_cyc <='1';
s_stb <='0';
FIFOrden_o <='0';
s_addrIncrement <='1';
s_WE <= s_WE;
s_addrLatch <='0';
s_sstFSMstate <= FIFO_CHECK;
when RETRY =>
s_FSMactive <='1';
s_cyc <='0';
s_stb <='0';
FIFOrden_o <='0';
s_addrIncrement <='0';
s_addrLatch <='0';
s_sstFSMstate <= CYC_ON;
when CYC_ON =>
s_FSMactive <='1';
s_cyc <='1';
s_stb <='0';
FIFOrden_o <='0';
s_addrIncrement <='0';
s_addrLatch <='0';
s_sstFSMstate <= STB_SET;
s_pipeCommActive <='1';
s_2eFSMstate <= DO_PIPELINED_COMM;
when OTHERS =>
s_FSMactive <='0';
s_cyc <='0';
s_stb <='0';
FIFOrden_o <='0';
s_addrIncrement <='0';
s_WE <= s_WE;
s_addrLatch <='0';
s_sstFSMstate <= IDLE;
s_pipeCommActive <='0';
s_2eFSMstate <= IDLE;
end case;
end if;
......@@ -247,13 +206,37 @@ begin
s_locAddr <= (others => '0');
elsif s_addrLatch='1' then
s_locAddr <= locAddr_i;
elsif s_addrIncrement='1' then
elsif s_pipeCommActive='1' then
s_locAddr <= s_locAddr + 8;
else
s_locAddr <= s_locAddr;
end if;
end if;
end process;
-- Beat counter
p_FIFObeatCounter: process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset='1' then
s_runningBeatCount <= (others => '0');
elsif s_pipeCommActive='1' then
s_runningBeatCount <= s_runningBeatCount + 1;
else
s_runningBeatCount <= s_runningBeatCount;
end if;
end if;
end process;
s_beatCountEnd <= '0' when s_runningBeatCount < beatCount_i else '1';
-- 2e write
FIFOrden <= '1' when s_pipeCommActive='1' and s_WE='1' and STALL_i='0' and writeFIFOempty_i='0' else '0';
s_STB <= '1' when s_pipeCommActive='1' and s_WE='1' and STALL_i='0' and writeFIFOempty_i='0' else '0';
end RTL;
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