Merge branch '7-add-ddr3-dependency' into 'master'

Resolve "Fix dependencies / submodules" Closes #7 See merge request be-cem-edl/fec/hardware-modules/svec!8

Merge branch '7-add-ddr3-dependency' into 'master'
Resolve "Fix dependencies / submodules" Closes #7 See merge request be-cem-edl/fec/hardware-modules/svec!8
af32268c · Dimitris Lampridis · c61facbe · f9da009f · af32268c · f692bc83
Commit af32268c authored Nov 30, 2022 by Dimitris Lampridis
13 changed files
--- a/.gitmodules
+++ b/.gitmodules
@@ -8,3 +8,9 @@
 [submodule "hdl/ip_cores/vme64x-core"]
 	path = hdl/ip_cores/vme64x-core
 	url = https://ohwr.org/project/vme64x-core.git
+[submodule "hdl/ip_cores/ddr3-sp6-core"]
+	path = hdl/ip_cores/ddr3-sp6-core
+	url = https://ohwr.org/project/ddr3-sp6-core.git
+[submodule "hdl/ip_cores/wr-cores"]
+	path = hdl/ip_cores/wr-cores
+	url = https://ohwr.org/project/wr-cores.git
--- a/ddr3-sp6-core @ f692bc83
+++ b/ddr3-sp6-core @ f692bc83
+Subproject commit f692bc83f42ffd54496f9e0da571c6f9dfcf2335
--- a/general-cores @ 1621d6d1
+++ b/general-cores @ 1621d6d1
-Subproject commit 6f2c1dbd5021debe6233c9495cb1b9d10f4a79de
+Subproject commit 1621d6d1f0c3040284136ce4b3b662269d6868d0
--- a/vme64x-core @ a0ca042e
+++ b/vme64x-core @ a0ca042e
-Subproject commit 1204aeca29ec3c72b6fa615976f000c664c7d152
+Subproject commit a0ca042e1f3c19a81c3594477c0c811ac761aaa4
--- a/wr-cores @ 3884a655
+++ b/wr-cores @ 3884a655
+Subproject commit 3884a65545907de3a0d41d549a4be9e6cccb4916
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
@@ -11,7 +11,7 @@ files = [
 try:
    # Assume this module is in fact a git submodule of a main project that
    # is in the same directory as general-cores...
-    exec(open("../../../" + "/general-cores/tools/gen_sourceid.py").read(),
+    exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
         None, {'project': 'svec_base'})
 except Exception as e:
    import os

--- a/hdl/rtl/svec_base_wr.vhd
+++ b/hdl/rtl/svec_base_wr.vhd
@@ -624,7 +624,7 @@ begin  -- architecture top
          metadata_data <= x"53564543";
        when x"2" =>
          -- Version
-          metadata_data <= x"02000001";
+          metadata_data <= x"03000000";
        when x"3" =>
          -- BOM
          metadata_data <= x"fffe0000";

--- a/hdl/syn/common/svec_base_common.ucf
+++ b/hdl/syn/common/svec_base_common.ucf
@@ -227,22 +227,22 @@ NET "*/gc_reset_async_in" TIG;
 NET "inst_svec_base/clk_sys_62m5" TNM_NET = sys_clk;
 NET "inst_svec_base/clk_ref_125m" TNM_NET = ref_clk;

-TIMEGRP "ref_sync_ffs"  = "sync_ffs" EXCEPT "ref_clk";
-TIMEGRP "sys_sync_ffs"  = "sync_ffs" EXCEPT "sys_clk";
-
 # Exceptions for crossings via gc_sync_ffs

 NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";

-#TIMESPEC TS_ref_sync_ffs  = FROM ref_clk TO "sys_sync_ffs"  TIG;
-#TIMESPEC TS_sys_sync_ffs  = FROM sys_clk TO "sys_sync_ffs"  TIG;
+TIMEGRP "ref_sync_ffs"  = "sync_ffs" EXCEPT "ref_clk";
+TIMEGRP "sys_sync_ffs"  = "sync_ffs" EXCEPT "sys_clk";
+
+TIMESPEC TS_ref_sync_ffs  = FROM ref_clk TO "sys_sync_ffs"  TIG;
+TIMESPEC TS_sys_sync_ffs  = FROM sys_clk TO "sys_sync_ffs"  TIG;

 # Exceptions for crossings via gc_sync_register

 NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";

-#TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "ref_clk";
-#TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
+TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "ref_clk";
+TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";

-#TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "ref_sync_reg"  8ns  DATAPATHONLY;
-#TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg"  16ns DATAPATHONLY;
+TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "ref_sync_reg"  8ns  DATAPATHONLY;
+TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg"  16ns DATAPATHONLY;
--- a/hdl/syn/common/svec_base_ddr_common.ucf
+++ b/hdl/syn/common/svec_base_ddr_common.ucf
@@ -7,7 +7,7 @@
 NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/c?_pll_lock"                                     TIG;
 NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
 NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL"  TIG;
-NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ"   TIG;
+#NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ"   TIG;

 #----------------------------------------
 # Asynchronous resets

--- a/hdl/syn/golden/Manifest.py
+++ b/hdl/syn/golden/Manifest.py
@@ -10,6 +10,11 @@ action = "synthesis"
 if locals().get('fetchto', None) is None:
  fetchto = "../../ip_cores"

+# Ideally this should be done by hdlmake itself, to allow downstream Manifests to be able to use the
+# fetchto variable independent of where those Manifests reside in the filesystem.
+import os
+fetchto = os.path.abspath(fetchto)
+
 syn_device = "xc6slx150t"
 syn_grade = "-3"
 syn_package = "fgg900"

--- a/hdl/syn/golden/syn_extra_steps.tcl
+++ b/hdl/syn/golden/syn_extra_steps.tcl
@@ -27,6 +27,9 @@ xilinx::project set "Register Duplication Map" "On"
 #xilinx::project set "Placer Extra Effort Map" "Normal"
 #xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"

+# Needed because some timegroup constraints are too generic and do not exist in the golden
+xilinx::project set "Allow Unmatched Timing Group Constraints" TRUE
+
 xilinx::project save

 xilinx::project close
--- a/hdl/syn/golden_wr/Manifest.py
+++ b/hdl/syn/golden_wr/Manifest.py
@@ -10,6 +10,11 @@ action = "synthesis"
 if locals().get('fetchto', None) is None:
  fetchto = "../../ip_cores"

+# Ideally this should be done by hdlmake itself, to allow downstream Manifests to be able to use the
+# fetchto variable independent of where those Manifests reside in the filesystem.
+import os
+fetchto = os.path.abspath(fetchto)
+
 syn_device = "xc6slx150t"
 syn_grade = "-3"
 syn_package = "fgg900"
@@ -20,7 +25,7 @@ syn_top = "svec_golden_wr"
 board = "svec"
 ctrls = ["bank4_64b_32b"]

-svec_template_ucf = ['ddr4', 'wr', 'gpio', 'led']
+svec_base_ucf = ['ddr4', 'wr', 'gpio', 'led']

 files = [ "buildinfo_pkg.vhd" ]


--- a/hdl/top/golden_wr/svec_golden_wr.vhd
+++ b/hdl/top/golden_wr/svec_golden_wr.vhd
@@ -208,7 +208,7 @@ architecture top of svec_golden_wr is

  signal pps_p : std_logic;
 begin
-  inst_svec_template: entity work.svec_template_wr
+  inst_svec_base: entity work.svec_base_wr
    generic map (
      g_with_vic => True,
      g_with_onewire => False,
@@ -327,7 +327,6 @@ begin
      ddr5_udqs_p_b => open,
      ddr5_we_n_o => open,
      pcbrev_i => pcbrev_i,
-  
      ddr4_clk_i => clk_sys_62m5,
      ddr4_rst_n_i => rst_sys_62m5_n,
      ddr4_wb_i.cyc => '0',
@@ -337,7 +336,6 @@ begin
      ddr4_wb_i.we => '0',
      ddr4_wb_i.dat => (63 downto 0 => '0'),
      ddr4_wb_o => open,
-  
      ddr5_clk_i => clk_sys_62m5,
      ddr5_rst_n_i => rst_sys_62m5_n,
      ddr5_wb_i.cyc => '0',
@@ -347,7 +345,6 @@ begin
      ddr5_wb_i.we => '0',
      ddr5_wb_i.dat => (63 downto 0 => '0'),
      ddr5_wb_o => open,
-  
      ddr4_wr_fifo_empty_o => open,
      ddr5_wr_fifo_empty_o => open,
      clk_sys_62m5_o => clk_sys_62m5,
@@ -355,7 +352,6 @@ begin
      clk_ref_125m_o => open,
      rst_ref_125m_n_o => open,
      irq_user_i => "",
-  
      wrf_src_o => open,
      wrf_src_i => open,
      wrf_snk_o => open,