Programming languages used in this repository

  •   VHDL
    46.39 %
  •   Verilog
    26.22 %
  •   SystemVerilog
    11.17 %
  •   C
    8.3 %
  •   Stata
    3.05 %
  •   HTML
    2.22 %
  •   Python
    1.07 %
  •   Lua
    1.03 %
  •   Makefile
    0.33 %
  •   Tcl
    0.18 %
  •   Shell
    0.05 %

Commit statistics for master Jun 08 - Oct 17

  • Total: 144 commits
  • Average per day: 0.1 commits
  • Authors: 7

Commits per day of month

Commits per weekday

Commits per day hour (UTC)