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Simple VME FMC Carrier SVEC
Commits
861bf346
Commit
861bf346
authored
Nov 28, 2022
by
Dimitris Lampridis
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hdl: delete golden rtl and testbench
These are obsolete
parent
af32268c
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9 changed files
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and
1040 deletions
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Manifest.py
hdl/rtl/golden/Manifest.py
+0
-5
golden_core.vhd
hdl/rtl/golden/golden_core.vhd
+0
-108
golden_core_pkg.vhd
hdl/rtl/golden/golden_core_pkg.vhd
+0
-43
golden_wb.vhd
hdl/rtl/golden/golden_wb.vhd
+0
-329
golden_wb.wb
hdl/rtl/golden/golden_wb.wb
+0
-173
golden_wbgen2_pkg.vhd
hdl/rtl/golden/golden_wbgen2_pkg.vhd
+0
-116
Manifest.py
hdl/testbench/golden/Manifest.py
+0
-13
main.sv
hdl/testbench/golden/main.sv
+0
-100
wave.do
hdl/testbench/golden/wave.do
+0
-153
No files found.
hdl/rtl/golden/Manifest.py
deleted
100644 → 0
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af32268c
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
files
=
[
"golden_core.vhd"
,
"golden_wbgen2_pkg.vhd"
,
"golden_wb.vhd"
,
"golden_core_pkg.vhd"
];
hdl/rtl/golden/golden_core.vhd
deleted
100644 → 0
View file @
af32268c
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
gld_wbgen2_pkg
.
all
;
entity
golden_core
is
generic
(
g_slot_count
:
integer
range
1
to
4
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
fmc_scl_o
:
out
std_logic_vector
(
g_slot_count
-1
downto
0
);
fmc_sda_o
:
out
std_logic_vector
(
g_slot_count
-1
downto
0
);
fmc_scl_i
:
in
std_logic_vector
(
g_slot_count
-1
downto
0
);
fmc_sda_i
:
in
std_logic_vector
(
g_slot_count
-1
downto
0
);
fmc_prsnt_n_i
:
in
std_logic_vector
(
g_slot_count
-1
downto
0
)
);
end
golden_core
;
architecture
rtl
of
golden_core
is
component
golden_wb
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
regs_i
:
in
t_gld_in_registers
;
regs_o
:
out
t_gld_out_registers
);
end
component
;
signal
regs_in
:
t_gld_in_registers
;
signal
regs_out
:
t_gld_out_registers
;
begin
-- rtl
regs_in
.
csr_slot_count_i
<=
std_logic_vector
(
to_unsigned
(
g_slot_count
,
4
));
U_WB_Slave
:
golden_wb
port
map
(
rst_n_i
=>
rst_n_i
,
clk_sys_i
=>
clk_sys_i
,
wb_adr_i
=>
slave_i
.
adr
(
4
downto
2
),
wb_dat_i
=>
slave_i
.
dat
,
wb_dat_o
=>
slave_o
.
dat
,
wb_cyc_i
=>
slave_i
.
cyc
,
wb_sel_i
=>
slave_i
.
sel
,
wb_stb_i
=>
slave_i
.
stb
,
wb_we_i
=>
slave_i
.
we
,
wb_ack_o
=>
slave_o
.
ack
,
wb_stall_o
=>
slave_o
.
stall
,
regs_i
=>
regs_in
,
regs_o
=>
regs_out
);
gen0
:
if
(
g_slot_count
>=
1
)
generate
fmc_scl_o
(
0
)
<=
regs_out
.
i2cr0_scl_out_o
;
fmc_sda_o
(
0
)
<=
regs_out
.
i2cr0_sda_out_o
;
regs_in
.
i2cr0_scl_in_i
<=
fmc_scl_i
(
0
);
regs_in
.
i2cr0_sda_in_i
<=
fmc_sda_i
(
0
);
regs_in
.
csr_fmc_present_i
(
0
)
<=
not
fmc_prsnt_n_i
(
0
);
end
generate
gen0
;
gen1
:
if
(
g_slot_count
>=
2
)
generate
fmc_scl_o
(
1
)
<=
regs_out
.
i2cr1_scl_out_o
;
fmc_sda_o
(
1
)
<=
regs_out
.
i2cr1_sda_out_o
;
regs_in
.
i2cr1_scl_in_i
<=
fmc_scl_i
(
1
);
regs_in
.
i2cr1_sda_in_i
<=
fmc_sda_i
(
1
);
regs_in
.
csr_fmc_present_i
(
1
)
<=
not
fmc_prsnt_n_i
(
1
);
end
generate
gen1
;
gen2
:
if
(
g_slot_count
>=
3
)
generate
fmc_scl_o
(
2
)
<=
regs_out
.
i2cr2_scl_out_o
;
fmc_sda_o
(
2
)
<=
regs_out
.
i2cr2_sda_out_o
;
regs_in
.
i2cr2_scl_in_i
<=
fmc_scl_i
(
2
);
regs_in
.
i2cr2_sda_in_i
<=
fmc_sda_i
(
2
);
regs_in
.
csr_fmc_present_i
(
2
)
<=
not
fmc_prsnt_n_i
(
2
);
end
generate
gen2
;
gen3
:
if
(
g_slot_count
>=
4
)
generate
fmc_scl_o
(
3
)
<=
regs_out
.
i2cr3_scl_out_o
;
fmc_sda_o
(
3
)
<=
regs_out
.
i2cr3_sda_out_o
;
regs_in
.
i2cr3_scl_in_i
<=
fmc_scl_i
(
3
);
regs_in
.
i2cr3_sda_in_i
<=
fmc_sda_i
(
3
);
regs_in
.
csr_fmc_present_i
(
3
)
<=
not
fmc_prsnt_n_i
(
3
);
end
generate
gen3
;
end
rtl
;
hdl/rtl/golden/golden_core_pkg.vhd
deleted
100644 → 0
View file @
af32268c
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
golden_core_pkg
is
component
golden_core
generic
(
g_slot_count
:
integer
range
1
to
4
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
fmc_scl_o
:
out
std_logic_vector
(
g_slot_count
-1
downto
0
);
fmc_sda_o
:
out
std_logic_vector
(
g_slot_count
-1
downto
0
);
fmc_scl_i
:
in
std_logic_vector
(
g_slot_count
-1
downto
0
);
fmc_sda_i
:
in
std_logic_vector
(
g_slot_count
-1
downto
0
);
fmc_prsnt_n_i
:
in
std_logic_vector
(
g_slot_count
-1
downto
0
));
end
component
;
constant
c_xwb_golden_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"7"
,
-- 8/16/32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"00000000000000ff"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"676f6c64"
,
version
=>
x"00000001"
,
date
=>
x"20130516"
,
name
=>
"WB-Golden-Core "
)));
end
golden_core_pkg
;
hdl/rtl/golden/golden_wb.vhd
deleted
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View file @
af32268c
This diff is collapsed.
Click to expand it.
hdl/rtl/golden/golden_wb.wb
deleted
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af32268c
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Golden Bitstream WB Slave";
description = "A universal Golden Bitstream core for FMC carriers. Supports detection of up to 4 mezzanines";
hdl_entity = "golden_wb";
prefix = "gld";
reg {
name = "Control/Status reg";
prefix = "CSR";
field {
name = "Number of FMC slots";
description = "Number of FMC slots provided by this carrier";
prefix = "SLOT_COUNT";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FMC presence line status";
description = "State of presence lines in the respective slots (1 = mezzanine inserted). Bit N = mezzanine (N+1).";
prefix = "FMC_PRESENT";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I2C bitbanged IO register for mezzanine 0";
prefix = "I2CR0";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I2C bitbanged IO register for mezzanine 1";
prefix = "I2CR1";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I2C bitbanged IO register for mezzanine 2";
prefix = "I2CR2";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I2C bitbanged IO register for mezzanine 3";
prefix = "I2CR3";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
\ No newline at end of file
hdl/rtl/golden/golden_wbgen2_pkg.vhd
deleted
100644 → 0
View file @
af32268c
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Golden Bitstream WB Slave
---------------------------------------------------------------------------------------
-- File : golden_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from golden_wb.wb
-- Created : Mon Feb 3 14:32:23 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE golden_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
package
gld_wbgen2_pkg
is
-- Input registers (user design -> WB slave)
type
t_gld_in_registers
is
record
csr_slot_count_i
:
std_logic_vector
(
3
downto
0
);
csr_fmc_present_i
:
std_logic_vector
(
3
downto
0
);
i2cr0_scl_in_i
:
std_logic
;
i2cr0_sda_in_i
:
std_logic
;
i2cr1_scl_in_i
:
std_logic
;
i2cr1_sda_in_i
:
std_logic
;
i2cr2_scl_in_i
:
std_logic
;
i2cr2_sda_in_i
:
std_logic
;
i2cr3_scl_in_i
:
std_logic
;
i2cr3_sda_in_i
:
std_logic
;
end
record
;
constant
c_gld_in_registers_init_value
:
t_gld_in_registers
:
=
(
csr_slot_count_i
=>
(
others
=>
'0'
),
csr_fmc_present_i
=>
(
others
=>
'0'
),
i2cr0_scl_in_i
=>
'0'
,
i2cr0_sda_in_i
=>
'0'
,
i2cr1_scl_in_i
=>
'0'
,
i2cr1_sda_in_i
=>
'0'
,
i2cr2_scl_in_i
=>
'0'
,
i2cr2_sda_in_i
=>
'0'
,
i2cr3_scl_in_i
=>
'0'
,
i2cr3_sda_in_i
=>
'0'
);
-- Output registers (WB slave -> user design)
type
t_gld_out_registers
is
record
i2cr0_scl_out_o
:
std_logic
;
i2cr0_sda_out_o
:
std_logic
;
i2cr1_scl_out_o
:
std_logic
;
i2cr1_sda_out_o
:
std_logic
;
i2cr2_scl_out_o
:
std_logic
;
i2cr2_sda_out_o
:
std_logic
;
i2cr3_scl_out_o
:
std_logic
;
i2cr3_sda_out_o
:
std_logic
;
end
record
;
constant
c_gld_out_registers_init_value
:
t_gld_out_registers
:
=
(
i2cr0_scl_out_o
=>
'0'
,
i2cr0_sda_out_o
=>
'0'
,
i2cr1_scl_out_o
=>
'0'
,
i2cr1_sda_out_o
=>
'0'
,
i2cr2_scl_out_o
=>
'0'
,
i2cr2_sda_out_o
=>
'0'
,
i2cr3_scl_out_o
=>
'0'
,
i2cr3_sda_out_o
=>
'0'
);
function
"or"
(
left
,
right
:
t_gld_in_registers
)
return
t_gld_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
end
package
;
package
body
gld_wbgen2_pkg
is
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
is
begin
if
x
=
'1'
then
return
'1'
;
else
return
'0'
;
end
if
;
end
function
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
begin
for
i
in
0
to
x
'length
-1
loop
if
(
x
(
i
)
=
'X'
or
x
(
i
)
=
'U'
)
then
tmp
(
i
):
=
'0'
;
else
tmp
(
i
):
=
x
(
i
);
end
if
;
end
loop
;
return
tmp
;
end
function
;
function
"or"
(
left
,
right
:
t_gld_in_registers
)
return
t_gld_in_registers
is
variable
tmp
:
t_gld_in_registers
;
begin
tmp
.
csr_slot_count_i
:
=
f_x_to_zero
(
left
.
csr_slot_count_i
)
or
f_x_to_zero
(
right
.
csr_slot_count_i
);
tmp
.
csr_fmc_present_i
:
=
f_x_to_zero
(
left
.
csr_fmc_present_i
)
or
f_x_to_zero
(
right
.
csr_fmc_present_i
);
tmp
.
i2cr0_scl_in_i
:
=
f_x_to_zero
(
left
.
i2cr0_scl_in_i
)
or
f_x_to_zero
(
right
.
i2cr0_scl_in_i
);
tmp
.
i2cr0_sda_in_i
:
=
f_x_to_zero
(
left
.
i2cr0_sda_in_i
)
or
f_x_to_zero
(
right
.
i2cr0_sda_in_i
);
tmp
.
i2cr1_scl_in_i
:
=
f_x_to_zero
(
left
.
i2cr1_scl_in_i
)
or
f_x_to_zero
(
right
.
i2cr1_scl_in_i
);
tmp
.
i2cr1_sda_in_i
:
=
f_x_to_zero
(
left
.
i2cr1_sda_in_i
)
or
f_x_to_zero
(
right
.
i2cr1_sda_in_i
);
tmp
.
i2cr2_scl_in_i
:
=
f_x_to_zero
(
left
.
i2cr2_scl_in_i
)
or
f_x_to_zero
(
right
.
i2cr2_scl_in_i
);
tmp
.
i2cr2_sda_in_i
:
=
f_x_to_zero
(
left
.
i2cr2_sda_in_i
)
or
f_x_to_zero
(
right
.
i2cr2_sda_in_i
);
tmp
.
i2cr3_scl_in_i
:
=
f_x_to_zero
(
left
.
i2cr3_scl_in_i
)
or
f_x_to_zero
(
right
.
i2cr3_scl_in_i
);
tmp
.
i2cr3_sda_in_i
:
=
f_x_to_zero
(
left
.
i2cr3_sda_in_i
)
or
f_x_to_zero
(
right
.
i2cr3_sda_in_i
);
return
tmp
;
end
function
;
end
package
body
;
hdl/testbench/golden/Manifest.py
deleted
100644 → 0
View file @
af32268c
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
action
=
"simulation"
target
=
"xilinx"
fetchto
=
"../../ip_cores"
vlog_opt
=
"+incdir+../../sim/vme64x_bfm +incdir+../../sim/wb"
files
=
[
"main.sv"
]
modules
=
{
"local"
:
[
"../../top/golden"
]
}
hdl/testbench/golden/main.sv
deleted
100644 → 0
View file @
af32268c
`include
"vme64x_bfm.svh"
`include
"svec_vme_buffers.svh"
`include
"../regs/golden_regs.vh"
module
main
;
reg
rst_n
=
0
;
reg
clk_20m
=
0
;
always
#
25
ns
clk_20m
<=
~
clk_20m
;
initial
begin
repeat
(
20
)
@
(
posedge
clk_20m
)
;
rst_n
=
1
;
end
IVME64X
VME
(
rst_n
)
;
`DECLARE_VME_BUFFERS
(
VME
.
slave
)
;
svec_top
DUT
(
.
clk_20m_vcxo_i
(
clk_20m
)
,
.
rst_n_i
(
rst_n
)
,
`WIRE_VME_PINS
(
8
)
)
;
task
automatic
config_vme_function
(
ref
CBusAccessor_VME64x
acc
,
input
int
func
,
uint64_t
base
,
int
am
)
;
uint64_t
addr
=
'h7ff63
+
func
*
'h10
;
uint64_t
val
=
(
base
)
|
(
am
<<
2
)
;
$
display
(
"Func%d ADER=0x%x"
,
func
,
val
)
;
acc
.
write
(
addr
+
0
,
(
val
>>
24
)
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
addr
+
4
,
(
val
>>
16
)
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
addr
+
8
,
(
val
>>
8
)
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
addr
+
12
,
(
val
>>
0
)
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
endtask
// config_vme_function
task
automatic
init_vme64x_core
(
ref
CBusAccessor_VME64x
acc
)
;
uint64_t
rv
;
/* map func0 to 0x80000000, A32 */
config_vme_function
(
acc
,
0
,
'h80000000
,
'h09
)
;
/* map func1 to 0xc00000, A24 */
config_vme_function
(
acc
,
1
,
'hc00000
,
'h39
)
;
acc
.
write
(
'h7ff33
,
1
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7fffb
,
'h10
,
CR_CSR
|
A32
|
D08Byte3
)
;
/* enable module (BIT_SET = 0x10) */
acc
.
set_default_modifiers
(
A24
|
D32
|
SINGLE
)
;
endtask
// init_vme64x_core
initial
begin
uint64_t
d
;
int
i
,
result
;
CBusAccessor_VME64x
acc
=
new
(
VME
.
master
)
;
#
20u
s
;
init_vme64x_core
(
acc
)
;
// acc.read('h80000000, d, A32|SINGLE|D32);
// $display("Read0: %x\n", d);
$
display
(
"pre-read"
)
;
acc
.
read
(
'hc00000
,
d
,
A24
|
SINGLE
|
D32
)
;
$
display
(
"Read0: %x
\n
"
,
d
)
;
acc
.
read
(
'h80000000
,
d
,
A32
|
SINGLE
|
D32
)
;
$
display
(
"Read1: %x
\n
"
,
d
)
;
/*
acc.write('h80010000, d, A24|SINGLE|D32);
acc.read('h80010000, d, A24|SINGLE|D32);
acc.write('h80010000 + `ADDR_GLD_I2CR0, ~`GLD_I2CR0_SCL_OUT, A24|SINGLE|D32);
acc.write('h80010000 + `ADDR_GLD_I2CR0, ~`GLD_I2CR0_SDA_OUT, A24|SINGLE|D32);
acc.write('h810000 + `ADDR_GLD_I2CR1, ~`GLD_I2CR0_SCL_OUT, A24|SINGLE|D32);
acc.write('h810000 + `ADDR_GLD_I2CR1, ~`GLD_I2CR0_SDA_OUT, A24|SINGLE|D32);
$display("Read1: %x\n", d);
*/
end
endmodule
// main
hdl/testbench/golden/wave.do
deleted
100644 → 0
View file @
af32268c
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