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Simple VME FMC Carrier SVEC
Commit 861bf346 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: delete golden rtl and testbench 

These are obsolete
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hdl/rtl/golden/Manifest.py deleted 100644 → 0
View file @ af32268c
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
files = ["golden_core.vhd", "golden_wbgen2_pkg.vhd", "golden_wb.vhd", "golden_core_pkg.vhd"];
hdl/rtl/golden/golden_core.vhd deleted 100644 → 0
View file @ af32268c
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.gld_wbgen2_pkg.all;
entity golden_core is
generic(
g_slot_count : integer range 1 to 4);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
fmc_scl_o : out std_logic_vector(g_slot_count-1 downto 0);
fmc_sda_o : out std_logic_vector(g_slot_count-1 downto 0);
fmc_scl_i : in std_logic_vector(g_slot_count-1 downto 0);
fmc_sda_i : in std_logic_vector(g_slot_count-1 downto 0);
fmc_prsnt_n_i : in std_logic_vector(g_slot_count-1 downto 0)
);
end golden_core;
architecture rtl of golden_core is
component golden_wb
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_gld_in_registers;
regs_o : out t_gld_out_registers);
end component;
signal regs_in : t_gld_in_registers;
signal regs_out : t_gld_out_registers;
begin -- rtl
regs_in.csr_slot_count_i <= std_logic_vector(to_unsigned(g_slot_count, 4));
U_WB_Slave : golden_wb
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => slave_i.adr(4 downto 2),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
regs_i => regs_in,
regs_o => regs_out);
gen0 : if(g_slot_count >= 1) generate
fmc_scl_o(0) <= regs_out.i2cr0_scl_out_o;
fmc_sda_o(0) <= regs_out.i2cr0_sda_out_o;
regs_in.i2cr0_scl_in_i <= fmc_scl_i(0);
regs_in.i2cr0_sda_in_i <= fmc_sda_i(0);
regs_in.csr_fmc_present_i(0) <= not fmc_prsnt_n_i(0);
end generate gen0;
gen1 : if(g_slot_count >= 2) generate
fmc_scl_o(1) <= regs_out.i2cr1_scl_out_o;
fmc_sda_o(1) <= regs_out.i2cr1_sda_out_o;
regs_in.i2cr1_scl_in_i <= fmc_scl_i(1);
regs_in.i2cr1_sda_in_i <= fmc_sda_i(1);
regs_in.csr_fmc_present_i(1) <= not fmc_prsnt_n_i(1);
end generate gen1;
gen2 : if(g_slot_count >= 3) generate
fmc_scl_o(2) <= regs_out.i2cr2_scl_out_o;
fmc_sda_o(2) <= regs_out.i2cr2_sda_out_o;
regs_in.i2cr2_scl_in_i <= fmc_scl_i(2);
regs_in.i2cr2_sda_in_i <= fmc_sda_i(2);
regs_in.csr_fmc_present_i(2) <= not fmc_prsnt_n_i(2);
end generate gen2;
gen3 : if(g_slot_count >= 4) generate
fmc_scl_o(3) <= regs_out.i2cr3_scl_out_o;
fmc_sda_o(3) <= regs_out.i2cr3_sda_out_o;
regs_in.i2cr3_scl_in_i <= fmc_scl_i(3);
regs_in.i2cr3_sda_in_i <= fmc_sda_i(3);
regs_in.csr_fmc_present_i(3) <= not fmc_prsnt_n_i(3);
end generate gen3;
end rtl;
hdl/rtl/golden/golden_core_pkg.vhd deleted 100644 → 0
View file @ af32268c
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package golden_core_pkg is
component golden_core
generic (
g_slot_count : integer range 1 to 4);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
fmc_scl_o : out std_logic_vector(g_slot_count-1 downto 0);
fmc_sda_o : out std_logic_vector(g_slot_count-1 downto 0);
fmc_scl_i : in std_logic_vector(g_slot_count-1 downto 0);
fmc_sda_i : in std_logic_vector(g_slot_count-1 downto 0);
fmc_prsnt_n_i : in std_logic_vector(g_slot_count-1 downto 0));
end component;
constant c_xwb_golden_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"676f6c64",
version => x"00000001",
date => x"20130516",
name => "WB-Golden-Core ")));
end golden_core_pkg;
hdl/rtl/golden/golden_wb.vhd deleted 100644 → 0
View file @ af32268c
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Golden Bitstream WB Slave
---------------------------------------------------------------------------------------
-- File : golden_wb.vhd
-- Author : auto-generated by wbgen2 from golden_wb.wb
-- Created : Mon Feb 3 14:32:23 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE golden_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gld_wbgen2_pkg.all;
entity golden_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_gld_in_registers;
regs_o : out t_gld_out_registers
);
end golden_wb;
architecture syn of golden_wb is
signal gld_i2cr0_scl_out_int : std_logic ;
signal gld_i2cr0_sda_out_int : std_logic ;
signal gld_i2cr1_scl_out_int : std_logic ;
signal gld_i2cr1_sda_out_int : std_logic ;
signal gld_i2cr2_scl_out_int : std_logic ;
signal gld_i2cr2_sda_out_int : std_logic ;
signal gld_i2cr3_scl_out_int : std_logic ;
signal gld_i2cr3_sda_out_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
gld_i2cr0_scl_out_int <= '1';
gld_i2cr0_sda_out_int <= '1';
gld_i2cr1_scl_out_int <= '1';
gld_i2cr1_sda_out_int <= '1';
gld_i2cr2_scl_out_int <= '1';
gld_i2cr2_sda_out_int <= '1';
gld_i2cr3_scl_out_int <= '1';
gld_i2cr3_sda_out_int <= '1';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= regs_i.csr_slot_count_i;
rddata_reg(7 downto 4) <= regs_i.csr_fmc_present_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
gld_i2cr0_scl_out_int <= wrdata_reg(0);
gld_i2cr0_sda_out_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= gld_i2cr0_scl_out_int;
rddata_reg(1) <= gld_i2cr0_sda_out_int;
rddata_reg(2) <= regs_i.i2cr0_scl_in_i;
rddata_reg(3) <= regs_i.i2cr0_sda_in_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
gld_i2cr1_scl_out_int <= wrdata_reg(0);
gld_i2cr1_sda_out_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= gld_i2cr1_scl_out_int;
rddata_reg(1) <= gld_i2cr1_sda_out_int;
rddata_reg(2) <= regs_i.i2cr1_scl_in_i;
rddata_reg(3) <= regs_i.i2cr1_sda_in_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (wb_we_i = '1') then
gld_i2cr2_scl_out_int <= wrdata_reg(0);
gld_i2cr2_sda_out_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= gld_i2cr2_scl_out_int;
rddata_reg(1) <= gld_i2cr2_sda_out_int;
rddata_reg(2) <= regs_i.i2cr2_scl_in_i;
rddata_reg(3) <= regs_i.i2cr2_sda_in_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
gld_i2cr3_scl_out_int <= wrdata_reg(0);
gld_i2cr3_sda_out_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= gld_i2cr3_scl_out_int;
rddata_reg(1) <= gld_i2cr3_sda_out_int;
rddata_reg(2) <= regs_i.i2cr3_scl_in_i;
rddata_reg(3) <= regs_i.i2cr3_sda_in_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Number of FMC slots
-- FMC presence line status
-- SCL Line out
regs_o.i2cr0_scl_out_o <= gld_i2cr0_scl_out_int;
-- SDA Line out
regs_o.i2cr0_sda_out_o <= gld_i2cr0_sda_out_int;
-- SCL Line in
-- SDA Line in
-- SCL Line out
regs_o.i2cr1_scl_out_o <= gld_i2cr1_scl_out_int;
-- SDA Line out
regs_o.i2cr1_sda_out_o <= gld_i2cr1_sda_out_int;
-- SCL Line in
-- SDA Line in
-- SCL Line out
regs_o.i2cr2_scl_out_o <= gld_i2cr2_scl_out_int;
-- SDA Line out
regs_o.i2cr2_sda_out_o <= gld_i2cr2_sda_out_int;
-- SCL Line in
-- SDA Line in
-- SCL Line out
regs_o.i2cr3_scl_out_o <= gld_i2cr3_scl_out_int;
-- SDA Line out
regs_o.i2cr3_sda_out_o <= gld_i2cr3_sda_out_int;
-- SCL Line in
-- SDA Line in
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/rtl/golden/golden_wb.wb deleted 100644 → 0
View file @ af32268c
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Golden Bitstream WB Slave";
description = "A universal Golden Bitstream core for FMC carriers. Supports detection of up to 4 mezzanines";
hdl_entity = "golden_wb";
prefix = "gld";
reg {
name = "Control/Status reg";
prefix = "CSR";
field {
name = "Number of FMC slots";
description = "Number of FMC slots provided by this carrier";
prefix = "SLOT_COUNT";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FMC presence line status";
description = "State of presence lines in the respective slots (1 = mezzanine inserted). Bit N = mezzanine (N+1).";
prefix = "FMC_PRESENT";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I2C bitbanged IO register for mezzanine 0";
prefix = "I2CR0";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I2C bitbanged IO register for mezzanine 1";
prefix = "I2CR1";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I2C bitbanged IO register for mezzanine 2";
prefix = "I2CR2";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I2C bitbanged IO register for mezzanine 3";
prefix = "I2CR3";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
\ No newline at end of file
hdl/rtl/golden/golden_wbgen2_pkg.vhd deleted 100644 → 0
View file @ af32268c
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Golden Bitstream WB Slave
---------------------------------------------------------------------------------------
-- File : golden_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from golden_wb.wb
-- Created : Mon Feb 3 14:32:23 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE golden_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package gld_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_gld_in_registers is record
csr_slot_count_i : std_logic_vector(3 downto 0);
csr_fmc_present_i : std_logic_vector(3 downto 0);
i2cr0_scl_in_i : std_logic;
i2cr0_sda_in_i : std_logic;
i2cr1_scl_in_i : std_logic;
i2cr1_sda_in_i : std_logic;
i2cr2_scl_in_i : std_logic;
i2cr2_sda_in_i : std_logic;
i2cr3_scl_in_i : std_logic;
i2cr3_sda_in_i : std_logic;
end record;
constant c_gld_in_registers_init_value: t_gld_in_registers := (
csr_slot_count_i => (others => '0'),
csr_fmc_present_i => (others => '0'),
i2cr0_scl_in_i => '0',
i2cr0_sda_in_i => '0',
i2cr1_scl_in_i => '0',
i2cr1_sda_in_i => '0',
i2cr2_scl_in_i => '0',
i2cr2_sda_in_i => '0',
i2cr3_scl_in_i => '0',
i2cr3_sda_in_i => '0'
);
-- Output registers (WB slave -> user design)
type t_gld_out_registers is record
i2cr0_scl_out_o : std_logic;
i2cr0_sda_out_o : std_logic;
i2cr1_scl_out_o : std_logic;
i2cr1_sda_out_o : std_logic;
i2cr2_scl_out_o : std_logic;
i2cr2_sda_out_o : std_logic;
i2cr3_scl_out_o : std_logic;
i2cr3_sda_out_o : std_logic;
end record;
constant c_gld_out_registers_init_value: t_gld_out_registers := (
i2cr0_scl_out_o => '0',
i2cr0_sda_out_o => '0',
i2cr1_scl_out_o => '0',
i2cr1_sda_out_o => '0',
i2cr2_scl_out_o => '0',
i2cr2_sda_out_o => '0',
i2cr3_scl_out_o => '0',
i2cr3_sda_out_o => '0'
);
function "or" (left, right: t_gld_in_registers) return t_gld_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body gld_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_gld_in_registers) return t_gld_in_registers is
variable tmp: t_gld_in_registers;
begin
tmp.csr_slot_count_i := f_x_to_zero(left.csr_slot_count_i) or f_x_to_zero(right.csr_slot_count_i);
tmp.csr_fmc_present_i := f_x_to_zero(left.csr_fmc_present_i) or f_x_to_zero(right.csr_fmc_present_i);
tmp.i2cr0_scl_in_i := f_x_to_zero(left.i2cr0_scl_in_i) or f_x_to_zero(right.i2cr0_scl_in_i);
tmp.i2cr0_sda_in_i := f_x_to_zero(left.i2cr0_sda_in_i) or f_x_to_zero(right.i2cr0_sda_in_i);
tmp.i2cr1_scl_in_i := f_x_to_zero(left.i2cr1_scl_in_i) or f_x_to_zero(right.i2cr1_scl_in_i);
tmp.i2cr1_sda_in_i := f_x_to_zero(left.i2cr1_sda_in_i) or f_x_to_zero(right.i2cr1_sda_in_i);
tmp.i2cr2_scl_in_i := f_x_to_zero(left.i2cr2_scl_in_i) or f_x_to_zero(right.i2cr2_scl_in_i);
tmp.i2cr2_sda_in_i := f_x_to_zero(left.i2cr2_sda_in_i) or f_x_to_zero(right.i2cr2_sda_in_i);
tmp.i2cr3_scl_in_i := f_x_to_zero(left.i2cr3_scl_in_i) or f_x_to_zero(right.i2cr3_scl_in_i);
tmp.i2cr3_sda_in_i := f_x_to_zero(left.i2cr3_sda_in_i) or f_x_to_zero(right.i2cr3_sda_in_i);
return tmp;
end function;
end package body;
hdl/testbench/golden/Manifest.py deleted 100644 → 0
View file @ af32268c
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../sim/vme64x_bfm +incdir+../../sim/wb"
files = [ "main.sv" ]
modules = { "local" : [ "../../top/golden" ] }
hdl/testbench/golden/main.sv deleted 100644 → 0
View file @ af32268c
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
`include "../regs/golden_regs.vh"
module main;
reg rst_n = 0;
reg clk_20m = 0;
always #25ns clk_20m <= ~clk_20m;
initial begin
repeat(20) @(posedge clk_20m);
rst_n = 1;
end
IVME64X VME(rst_n);
`DECLARE_VME_BUFFERS(VME.slave);
svec_top
DUT (
.clk_20m_vcxo_i(clk_20m),
.rst_n_i(rst_n),
`WIRE_VME_PINS(8)
);
task automatic config_vme_function(ref CBusAccessor_VME64x acc, input int func, uint64_t base, int am);
uint64_t addr = 'h7ff63 + func * 'h10;
uint64_t val = (base) | (am << 2);
$display("Func%d ADER=0x%x", func, val);
acc.write(addr + 0, (val >> 24) & 'hff, CR_CSR|A32|D08Byte3);
acc.write(addr + 4, (val >> 16) & 'hff, CR_CSR|A32|D08Byte3);
acc.write(addr + 8, (val >> 8) & 'hff, CR_CSR|A32|D08Byte3);
acc.write(addr + 12, (val >> 0) & 'hff, CR_CSR|A32|D08Byte3);
endtask // config_vme_function
task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
uint64_t rv;
/* map func0 to 0x80000000, A32 */
config_vme_function(acc, 0, 'h80000000, 'h09);
/* map func1 to 0xc00000, A24 */
config_vme_function(acc, 1, 'hc00000, 'h39);
acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
acc.set_default_modifiers(A24 | D32 | SINGLE);
endtask // init_vme64x_core
initial begin
uint64_t d;
int i, result;
CBusAccessor_VME64x acc = new(VME.master);
#20us;
init_vme64x_core(acc);
// acc.read('h80000000, d, A32|SINGLE|D32);
// $display("Read0: %x\n", d);
$display("pre-read");
acc.read('hc00000, d, A24|SINGLE|D32);
$display("Read0: %x\n", d);
acc.read('h80000000, d, A32|SINGLE|D32);
$display("Read1: %x\n", d);
/*
acc.write('h80010000, d, A24|SINGLE|D32);
acc.read('h80010000, d, A24|SINGLE|D32);
acc.write('h80010000 + `ADDR_GLD_I2CR0, ~`GLD_I2CR0_SCL_OUT, A24|SINGLE|D32);
acc.write('h80010000 + `ADDR_GLD_I2CR0, ~`GLD_I2CR0_SDA_OUT, A24|SINGLE|D32);
acc.write('h810000 + `ADDR_GLD_I2CR1, ~`GLD_I2CR0_SCL_OUT, A24|SINGLE|D32);
acc.write('h810000 + `ADDR_GLD_I2CR1, ~`GLD_I2CR0_SDA_OUT, A24|SINGLE|D32);
$display("Read1: %x\n", d);
*/
end
endmodule // main
hdl/testbench/golden/wave.do deleted 100644 → 0
View file @ af32268c
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/clk_i
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/reset
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/decode
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/mainFSMreset
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Addr
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/AddrWidth
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Ader0
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Ader1
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Ader2
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Ader3
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Ader4
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Ader5
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Ader6
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Ader7
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Adem0
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Adem1
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Adem2
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Adem3
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Adem4
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Adem5
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Adem6
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Adem7
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/FunctMatch
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/DFS_o
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADEM
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER_64
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADEM_64
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_isprev_func64
add wave -noupdate -expand -group FuncMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/clk_i
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/reset
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/mainFSMreset
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Ader0
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Ader1
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Ader2
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Ader3
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Ader4
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Ader5
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Ader6
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Ader7
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmCap0
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmCap1
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmCap2
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmCap3
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmCap4
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmCap5
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmCap6
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmCap7
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/XAmCap0
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/XAmCap1
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/XAmCap2
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/XAmCap3
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/XAmCap4
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/XAmCap5
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/XAmCap6
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/XAmCap7
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Am
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/XAm
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/DFS_i
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/decode
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch
add wave -noupdate -expand -group AmMatch -radix hexadecimal -childformat {{/main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(0) -radix hexadecimal} {/main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(1) -radix hexadecimal} {/main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(2) -radix hexadecimal} {/main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(3) -radix hexadecimal} {/main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(4) -radix hexadecimal} {/main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(5) -radix hexadecimal} {/main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(6) -radix hexadecimal} {/main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(7) -radix hexadecimal}} -subitemconfig {/main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(0) {-radix hexadecimal} /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(1) {-radix hexadecimal} /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(2) {-radix hexadecimal} /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(3) {-radix hexadecimal} /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(4) {-radix hexadecimal} /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(5) {-radix hexadecimal} /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(6) {-radix hexadecimal} /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER(7) {-radix hexadecimal}} /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_ADER
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_AMCAP
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_FUNC_XAMCAP
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_amcap_match
add wave -noupdate -expand -group AmMatch -radix hexadecimal /main/DUT/U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/s_xamcap_match
add wave -noupdate -radix hexadecimal /main/rst_n
add wave -noupdate -radix hexadecimal /main/clk_20m
add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_out
add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_in
add wave -noupdate -radix hexadecimal /main/DUT/cnx_slave_out
add wave -noupdate -radix hexadecimal -childformat {{/main/DUT/cnx_slave_in(0) -radix hexadecimal}} -expand -subitemconfig {/main/DUT/cnx_slave_in(0) {-height 17 -radix hexadecimal}} /main/DUT/cnx_slave_in
add wave -noupdate -radix hexadecimal /main/DUT/clk_20m_vcxo_i
add wave -noupdate -radix hexadecimal /main/DUT/rst_n_i
add wave -noupdate -radix hexadecimal /main/DUT/VME_AS_n_i
add wave -noupdate -radix hexadecimal /main/DUT/VME_RST_n_i
add wave -noupdate -radix hexadecimal /main/DUT/VME_WRITE_n_i
add wave -noupdate -radix hexadecimal /main/DUT/VME_AM_i
add wave -noupdate -radix hexadecimal /main/DUT/VME_DS_n_i
add wave -noupdate -radix hexadecimal /main/DUT/VME_GA_i
add wave -noupdate -radix hexadecimal /main/DUT/VME_BERR_o
add wave -noupdate -radix hexadecimal /main/DUT/VME_DTACK_n_o
add wave -noupdate -radix hexadecimal /main/DUT/VME_RETRY_n_o
add wave -noupdate -radix hexadecimal /main/DUT/VME_RETRY_OE_o
add wave -noupdate -radix hexadecimal /main/DUT/VME_LWORD_n_b
add wave -noupdate -radix hexadecimal /main/DUT/VME_ADDR_b
add wave -noupdate -radix hexadecimal /main/DUT/VME_DATA_b
add wave -noupdate -radix hexadecimal /main/DUT/VME_BBSY_n_i
add wave -noupdate -radix hexadecimal /main/DUT/VME_IRQ_n_o
add wave -noupdate -radix hexadecimal /main/DUT/VME_IACK_n_i
add wave -noupdate -radix hexadecimal /main/DUT/VME_IACKIN_n_i
add wave -noupdate -radix hexadecimal /main/DUT/VME_IACKOUT_n_o
add wave -noupdate -radix hexadecimal /main/DUT/VME_DTACK_OE_o
add wave -noupdate -radix hexadecimal /main/DUT/VME_DATA_DIR_o
add wave -noupdate -radix hexadecimal /main/DUT/VME_DATA_OE_N_o
add wave -noupdate -radix hexadecimal /main/DUT/VME_ADDR_DIR_o
add wave -noupdate -radix hexadecimal /main/DUT/VME_ADDR_OE_N_o
add wave -noupdate -radix hexadecimal /main/DUT/fmc0_prsntm2c_n_i
add wave -noupdate -radix hexadecimal /main/DUT/fmc1_prsntm2c_n_i
add wave -noupdate -radix hexadecimal /main/DUT/fmc0_scl_b
add wave -noupdate -radix hexadecimal /main/DUT/fmc0_sda_b
add wave -noupdate -radix hexadecimal /main/DUT/fmc1_scl_b
add wave -noupdate -radix hexadecimal /main/DUT/fmc1_sda_b
add wave -noupdate -radix hexadecimal /main/DUT/U_Golden_Core/regs_in
add wave -noupdate -radix hexadecimal /main/DUT/U_Golden_Core/regs_out
add wave -noupdate -radix hexadecimal /main/DUT/tempid_dq_b
add wave -noupdate -radix hexadecimal /main/DUT/VME_DATA_b_out
add wave -noupdate -radix hexadecimal /main/DUT/VME_ADDR_b_out
add wave -noupdate -radix hexadecimal /main/DUT/VME_LWORD_n_b_out
add wave -noupdate -radix hexadecimal /main/DUT/VME_DATA_DIR_int
add wave -noupdate -radix hexadecimal /main/DUT/VME_ADDR_DIR_int
add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_out
add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_in
add wave -noupdate -radix hexadecimal /main/DUT/cnx_slave_out
add wave -noupdate -radix hexadecimal /main/DUT/cnx_slave_in
add wave -noupdate -radix hexadecimal /main/DUT/fd0_scl_out
add wave -noupdate -radix hexadecimal /main/DUT/fd0_scl_in
add wave -noupdate -radix hexadecimal /main/DUT/fd0_sda_out
add wave -noupdate -radix hexadecimal /main/DUT/fd0_sda_in
add wave -noupdate -radix hexadecimal /main/DUT/fd1_scl_out
add wave -noupdate -radix hexadecimal /main/DUT/fd1_scl_in
add wave -noupdate -radix hexadecimal /main/DUT/fd1_sda_out
add wave -noupdate -radix hexadecimal /main/DUT/fd1_sda_in
add wave -noupdate -radix hexadecimal /main/DUT/wrc_owr_en
add wave -noupdate -radix hexadecimal /main/DUT/wrc_owr_in
add wave -noupdate -radix hexadecimal /main/DUT/pllout_clk_fb_sys
add wave -noupdate -radix hexadecimal /main/DUT/pllout_clk_sys
add wave -noupdate -radix hexadecimal /main/DUT/clk_20m_vcxo_buf
add wave -noupdate -radix hexadecimal /main/DUT/clk_sys
add wave -noupdate -radix hexadecimal /main/DUT/local_reset_n
add wave -noupdate -radix hexadecimal -childformat {{/main/DUT/vme_master_out.cyc -radix hexadecimal} {/main/DUT/vme_master_out.stb -radix hexadecimal} {/main/DUT/vme_master_out.adr -radix hexadecimal} {/main/DUT/vme_master_out.sel -radix hexadecimal} {/main/DUT/vme_master_out.we -radix hexadecimal} {/main/DUT/vme_master_out.dat -radix hexadecimal}} -expand -subitemconfig {/main/DUT/vme_master_out.cyc {-height 17 -radix hexadecimal} /main/DUT/vme_master_out.stb {-height 17 -radix hexadecimal} /main/DUT/vme_master_out.adr {-height 17 -radix hexadecimal} /main/DUT/vme_master_out.sel {-height 17 -radix hexadecimal} /main/DUT/vme_master_out.we {-height 17 -radix hexadecimal} /main/DUT/vme_master_out.dat {-height 17 -radix hexadecimal}} /main/DUT/vme_master_out
add wave -noupdate -radix hexadecimal /main/DUT/vme_master_in
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {28970077 ps} 0}
configure wave -namecolwidth 177
configure wave -valuecolwidth 244
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {18189586 ps} {31885210 ps}
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