Skip to content

S
Simple VME FMC Carrier SVEC
Commit 37d6449f authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

svec7: proof of concept VME-serial bridge to save on FPGA pins

parent 29b98259
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 308 additions and 169 deletions
vme64x-core @ 143da27e
Subproject commit 6f359655ae8e9f1cab3f85d673f430b80692ed7b Subproject commit 143da27eb8ac717503823e447c4c3ea9e7e1313e
wr-cores @ 53dd7e43
Subproject commit 4482c478f29185f81dd45312f4f1ae2f28494957 Subproject commit 53dd7e430a1111c9a13ea799b4ba0972b046bd2c
hdl/rtl/svec7a/svec7_base_wr.vhd
View file @ 37d6449f
...@@ -107,12 +107,11 @@ entity svec7_base_wr is ...@@ -107,12 +107,11 @@ entity svec7_base_wr is
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
vme_sysreset_n_i : in std_logic; vme_sysreset_n_i : in std_logic;
sfpga_clk_o : out std_logic;
sfpga_rst_n_o : out std_logic; sfpga_clk_p_o : out std_logic;
sfpga_frame_o : out std_logic; sfpga_clk_n_o : out std_logic;
sfpga_d_o : out std_logic_vector(7 downto 0); sfpga_rx_i : in std_logic_vector(4 downto 0);
sfpga_frame_i : in std_logic := '0'; sfpga_tx_o : out std_logic_vector(4 downto 0);
sfpga_d_i : in std_logic_vector(7 downto 0) := x"00";
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -455,6 +454,11 @@ architecture top of svec7_base_wr is ...@@ -455,6 +454,11 @@ architecture top of svec7_base_wr is
attribute keep of clk_ref_125m : signal is "TRUE"; attribute keep of clk_ref_125m : signal is "TRUE";
attribute keep of ddr_rst : signal is "TRUE"; attribute keep of ddr_rst : signal is "TRUE";
signal sfpga_d_in : std_logic_vector(15 downto 0);
signal sfpga_frame_in : std_logic;
signal sfpga_d_out : std_logic_vector(15 downto 0);
signal sfpga_frame_out : std_logic;
begin -- architecture top begin -- architecture top
rst_sys_62m5 <= not rst_sys_62m5_n; rst_sys_62m5 <= not rst_sys_62m5_n;
...@@ -463,6 +467,24 @@ begin -- architecture top ...@@ -463,6 +467,24 @@ begin -- architecture top
-- VME interface -- VME interface
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_vme_serial_bridge: entity work.xvme64x_bridge_serdes
generic map (
g_mode => SLAVE,
g_platform => "spartan6",
g_SERDES_RX_DELAY_TAPS => 0,
g_CLOCK_PERIOD => 16)
port map (
clk_125m_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
bridge_d_i => sfpga_d_out,
bridge_frame_i => sfpga_frame_out,
bridge_d_o => sfpga_d_in,
bridge_frame_o => sfpga_frame_in,
ser_clk_p_o => sfpga_clk_p_o,
ser_clk_n_o => sfpga_clk_n_o,
ser_tx_o => sfpga_tx_o,
ser_rx_i => sfpga_rx_i);
cmp_vme_core : entity work.xvme64x_core_slave cmp_vme_core : entity work.xvme64x_core_slave
generic map ( generic map (
g_CLOCK_PERIOD => 16, g_CLOCK_PERIOD => 16,
...@@ -480,13 +502,11 @@ begin -- architecture top ...@@ -480,13 +502,11 @@ begin -- architecture top
wb_o => vme_wb_out, wb_o => vme_wb_out,
wb_i => vme_wb_in, wb_i => vme_wb_in,
bridge_clk_o => sfpga_clk_o, bridge_frame_o => sfpga_frame_out,
bridge_rst_n_o => sfpga_rst_n_o, bridge_d_o => sfpga_d_out,
bridge_d_i => sfpga_d_i, bridge_frame_i => sfpga_frame_in,
bridge_d_o => sfpga_d_o, bridge_d_i => sfpga_d_in,
bridge_frame_i => sfpga_frame_i,
bridge_frame_o => sfpga_frame_o,
int_i => irq_master); int_i => irq_master);
......
hdl/testbench/svec7_bridge/buildinfo_pkg.vhd
View file @ 37d6449f
...@@ -6,8 +6,8 @@ package buildinfo_pkg is ...@@ -6,8 +6,8 @@ package buildinfo_pkg is
constant buildinfo : string := constant buildinfo : string :=
"buildinfo:1" & LF "buildinfo:1" & LF
& "module:main" & LF & "module:main" & LF
& "commit:90348ce26bfdc3ee9b9477c26c91f74450f730db" & LF & "commit:29b9825929c1a5f0478675cbed6ab2b5916d9c5f" & LF
& "syntool:modelsim" & LF & "syntool:modelsim" & LF
& "syndate:2019-11-27, 17:39 CET" & LF & "syndate:2019-12-02, 11:30 CET" & LF
& "synauth:Tomasz Wlostowski" & LF; & "synauth:Tomasz Wlostowski" & LF;
end buildinfo_pkg; end buildinfo_pkg;
hdl/testbench/svec7_bridge/main.sv
View file @ 37d6449f
...@@ -44,22 +44,8 @@ module main; ...@@ -44,22 +44,8 @@ module main;
logic [4:0] slot_id = 5'h8; logic [4:0] slot_id = 5'h8;
wire [7:0] afpga_dout, afpga_din; wire [4:0] afpga_tx, afpga_rx;
wire afpga_fout, afpga_fin ; wire afpga_clk_p, afpga_clk_n;
reg [7:0] afpga_dout_delayed, afpga_din_delayed;
reg afpga_fout_delayed, afpga_fin_delayed ;
wire afpga_clk, afpga_rst_n;
always@(afpga_dout)
#1ns afpga_dout_delayed <= afpga_dout;
always@(afpga_din)
#1ns afpga_din_delayed <= afpga_din;
always@(afpga_fout)
#1ns afpga_fout_delayed <= afpga_fout;
always@(afpga_fin)
#1ns afpga_fin_delayed <= afpga_fin;
svec7_sfpga_top svec7_sfpga_top
...@@ -69,12 +55,11 @@ module main; ...@@ -69,12 +55,11 @@ module main;
DUT ( DUT (
.rst_n_i(rst_n), .rst_n_i(rst_n),
.lclk_i (clk_local), .lclk_i (clk_local),
.afpga_clk_i(afpga_clk),
.afpga_rst_n_i(afpga_rst_n), .afpga_clk_p_i(afpga_clk_p),
.afpga_d_i(afpga_dout_delayed), .afpga_clk_n_i(afpga_clk_n),
.afpga_d_o(afpga_din ), .afpga_tx_o(afpga_rx),
.afpga_frame_o(afpga_fin), .afpga_rx_i(afpga_tx),
.afpga_frame_i(afpga_fout_delayed),
.vme_as_n_i (VME_AS_n), .vme_as_n_i (VME_AS_n),
.vme_sysreset_n_i (VME_RST_n), .vme_sysreset_n_i (VME_RST_n),
.vme_write_n_i (VME_WRITE_n), .vme_write_n_i (VME_WRITE_n),
...@@ -116,13 +101,12 @@ module main; ...@@ -116,13 +101,12 @@ module main;
.clk_125m_gtp_n_i (clk_125m_pllref), .clk_125m_gtp_n_i (clk_125m_pllref),
.clk_125m_gtp_p_i (~clk_125m_pllref), .clk_125m_gtp_p_i (~clk_125m_pllref),
.sfpga_clk_o(afpga_clk),
.sfpga_rst_n_o(afpga_rst_n),
.sfpga_d_i(afpga_din_delayed ),
.sfpga_d_o(afpga_dout),
.sfpga_frame_o(afpga_fout),
.sfpga_frame_i(afpga_fin_delayed ),
.sfpga_clk_p_o(afpga_clk_p),
.sfpga_clk_n_o(afpga_clk_n),
.sfpga_tx_o(afpga_tx),
.sfpga_rx_i(afpga_rx),
.vme_sysreset_n_i(VME_RST_n), .vme_sysreset_n_i(VME_RST_n),
.fmc0_scl_b (), .fmc0_scl_b (),
...@@ -179,7 +163,7 @@ module main; ...@@ -179,7 +163,7 @@ module main;
acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3); acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3); acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3); acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3); acc.write('h7ff6f, 32, CR_CSR|A32|D08Byte3);
acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3); acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */ acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
...@@ -194,6 +178,10 @@ module main; ...@@ -194,6 +178,10 @@ module main;
initial begin initial begin
uint64_t d; uint64_t d;
uint64_t addr[1];
uint64_t data[] = new[512];
real t_start, t_end;
int i, result; int i, result;
...@@ -205,17 +193,28 @@ module main; ...@@ -205,17 +193,28 @@ module main;
// Display meta data // Display meta data
d = 'hdeadbeef; d = 'hdeadbeef;
acc.write('h80000000, d, A32|SINGLE|D32); acc.write('h80000000, d, A24|SINGLE|D32);
d = 'hcafebabe; d = 'hcafebabe;
acc.write('h80000004, d, A32|SINGLE|D32); acc.write('h80000004, d, A24|SINGLE|D32);
acc.read('h80000000, d, A32|SINGLE|D32); acc.read('h80000000, d, A24|SINGLE|D32);
$display("Rdbk[0] = %x", d); $display("Rdbk[0] = %x", d);
acc.read('h80000004, d, A32|SINGLE|D32); acc.read('h80000004, d, A24|SINGLE|D32);
$display("Rdbk[4] = %x", d); $display("Rdbk[4] = %x", d);
//$display("ddr status: %x", d); //$display("ddr status: %x", d);
addr[0] = 'h80001000;
t_start = real'($time) / real'( 1us );
acc.readm( addr, data, A32|MBLT|D32, result );
t_end = real'($time) / real'(1us);
$display("mblt : %d bytes / %.0f us = approx %.0f bytes / second", data.size() * 4, t_end-t_start, real'(data.size()) * 4 * 1e6/(t_end-t_start));
end end
......
hdl/testbench/svec7_bridge/wave.do
View file @ 37d6449f
This diff is collapsed.
hdl/top/svec7_sfpga/Manifest.py
View file @ 37d6449f
...@@ -3,6 +3,6 @@ files = [ "svec7_sfpga_top.vhd", "svec7_sfpga_top.ucf", "reset_gen.vhd", "svec7_ ...@@ -3,6 +3,6 @@ files = [ "svec7_sfpga_top.vhd", "svec7_sfpga_top.ucf", "reset_gen.vhd", "svec7_
fetchto = "../../ip_cores" fetchto = "../../ip_cores"
modules = { modules = {
"local" : ["../../rtl/bootloader" ], "local" : ["../../rtl/bootloader", "../../ip_cores/vme64x-core" ],
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git" ] "git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git" ]
} }
hdl/top/svec7_sfpga/svec7_sfpga_top.ucf
View file @ 37d6449f
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
# VME interface # VME interface
#---------------------------------------- #----------------------------------------
NET "vme_write_n_i" LOC = B1; NET "vme_write_n_i" LOC = B1;
NET "vme_rst_n_i" LOC = G6; #NET "vme_rst_n_i" LOC = G6;
#NET "vme_retry_oe_o" LOC = D3; #NET "vme_retry_oe_o" LOC = D3;
#NET "vme_retry_n_o" LOC = D1; #NET "vme_retry_n_o" LOC = D1;
NET "vme_lword_n_b" LOC = B3; NET "vme_lword_n_b" LOC = B3;
...@@ -29,7 +29,7 @@ NET "vme_addr_dir_o" LOC = B2; ...@@ -29,7 +29,7 @@ NET "vme_addr_dir_o" LOC = B2;
#NET "vme_irq_n_o[2]" LOC = E10; #NET "vme_irq_n_o[2]" LOC = E10;
#NET "vme_irq_n_o[1]" LOC = E8; #NET "vme_irq_n_o[1]" LOC = E8;
#NET "vme_irq_n_o[0]" LOC = E7; #NET "vme_irq_n_o[0]" LOC = E7;
NET "vme_ga_i[5]" LOC = A3; NET "vme_gap_i" LOC = A3;
NET "vme_ga_i[4]" LOC = A10; NET "vme_ga_i[4]" LOC = A10;
NET "vme_ga_i[3]" LOC = B10; NET "vme_ga_i[3]" LOC = B10;
NET "vme_ga_i[2]" LOC = A9; NET "vme_ga_i[2]" LOC = A9;
...@@ -119,7 +119,7 @@ NET "debugled_n_o[1]" LOC = L16; ...@@ -119,7 +119,7 @@ NET "debugled_n_o[1]" LOC = L16;
#IO standards #IO standards
NET "vme_write_n_i" IOSTANDARD="LVCMOS33"; NET "vme_write_n_i" IOSTANDARD="LVCMOS33";
NET "vme_rst_n_i" IOSTANDARD="LVCMOS33"; #NET "vme_rst_n_i" IOSTANDARD="LVCMOS33";
#NET "vme_retry_oe_o" IOSTANDARD="LVCMOS33"; #NET "vme_retry_oe_o" IOSTANDARD="LVCMOS33";
#NET "vme_retry_n_o" IOSTANDARD="LVCMOS33"; #NET "vme_retry_n_o" IOSTANDARD="LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD="LVCMOS33"; NET "vme_lword_n_b" IOSTANDARD="LVCMOS33";
...@@ -143,7 +143,7 @@ NET "vme_addr_dir_o" IOSTANDARD="LVCMOS33"; ...@@ -143,7 +143,7 @@ NET "vme_addr_dir_o" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[2]" IOSTANDARD="LVCMOS33"; #NET "vme_irq_n_o[2]" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[1]" IOSTANDARD="LVCMOS33"; #NET "vme_irq_n_o[1]" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[0]" IOSTANDARD="LVCMOS33"; #NET "vme_irq_n_o[0]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[5]" IOSTANDARD="LVCMOS33"; NET "vme_gap_i" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD="LVCMOS33"; NET "vme_ga_i[4]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD="LVCMOS33"; NET "vme_ga_i[3]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[2]" IOSTANDARD="LVCMOS33"; NET "vme_ga_i[2]" IOSTANDARD="LVCMOS33";
...@@ -243,11 +243,9 @@ NET "spi_miso_i" LOC = P10; ...@@ -243,11 +243,9 @@ NET "spi_miso_i" LOC = P10;
# Clocks/resets # Clocks/resets
NET "rst_n_i" LOC = E15; NET "rst_n_i" LOC = E15;
NET "lclk_n_i" LOC = H5; #NET "lclk_n_i" LOC = H5;
NET "rst_n_i" IOSTANDARD="LVCMOS33"; NET "rst_n_i" IOSTANDARD="LVCMOS33";
NET "lclk_n_i" IOSTANDARD="LVCMOS33"; #NET "lclk_n_i" IOSTANDARD="LVCMOS33";
NET "pll_ce_o" IOSTANDARD="LVCMOS33"; NET "pll_ce_o" IOSTANDARD="LVCMOS33";
NET "pll_ce_o" LOC=G14; NET "pll_ce_o" LOC=G14;
...@@ -261,6 +259,30 @@ NET "afpga_flash_mosi_i" IOSTANDARD=LVCMOS33; ...@@ -261,6 +259,30 @@ NET "afpga_flash_mosi_i" IOSTANDARD=LVCMOS33;
NET "afpga_flash_cs_n_i" IOSTANDARD=LVCMOS33; NET "afpga_flash_cs_n_i" IOSTANDARD=LVCMOS33;
NET "afpga_flash_miso_o" IOSTANDARD=LVCMOS33; NET "afpga_flash_miso_o" IOSTANDARD=LVCMOS33;
#Created by Constraints Editor (xc6slx9-ftg256-2) - 2014/01/15 NET "afpga_clk_p_i" IOSTANDARD=LVDS_33;
NET "lclk_n_i" TNM_NET = lclk_n_i;
TIMESPEC TS_lclk_n_i = PERIOD "lclk_n_i" 20 MHz HIGH 50%; NET "afpga_tx_o[0]" IOSTANDARD=SSTL3_I;
NET "afpga_tx_o[1]" IOSTANDARD=SSTL3_I;
NET "afpga_tx_o[2]" IOSTANDARD=SSTL3_I;
NET "afpga_tx_o[3]" IOSTANDARD=SSTL3_I;
NET "afpga_tx_o[4]" IOSTANDARD=SSTL3_I;
NET "afpga_rx_i[0]" IOSTANDARD=SSTL3_I;
NET "afpga_rx_i[1]" IOSTANDARD=SSTL3_I;
NET "afpga_rx_i[2]" IOSTANDARD=SSTL3_I;
NET "afpga_rx_i[3]" IOSTANDARD=SSTL3_I;
NET "afpga_rx_i[4]" IOSTANDARD=SSTL3_I;
NET "vme_iackout_n_o" IOSTANDARD=LVCMOS33;
NET "vme_berr_o" IOSTANDARD=LVCMOS33;
NET "vme_retry_n_o" IOSTANDARD=LVCMOS33;
NET "vme_irq_o[7]" IOSTANDARD=LVCMOS33;
NET "vme_irq_o[6]" IOSTANDARD=LVCMOS33;
NET "vme_irq_o[5]" IOSTANDARD=LVCMOS33;
NET "vme_irq_o[4]" IOSTANDARD=LVCMOS33;
NET "vme_irq_o[3]" IOSTANDARD=LVCMOS33;
NET "vme_irq_o[2]" IOSTANDARD=LVCMOS33;
NET "vme_irq_o[1]" IOSTANDARD=LVCMOS33;
NET "vme_retry_oe_o" IOSTANDARD=LVCMOS33;
#Created by Constraints Editor (xc6slx9-ftg256-2) - 2019/11/28
NET "lclk_i" TNM_NET = lclk_i;
TIMESPEC TS_lclk_i = PERIOD "lclk_i" 50 ns HIGH 50%;
hdl/top/svec7_sfpga/svec7_sfpga_top.vhd
View file @ 37d6449f
...@@ -91,14 +91,11 @@ entity svec7_sfpga_top is ...@@ -91,14 +91,11 @@ entity svec7_sfpga_top is
vme_noga_i : in std_logic_vector(4 downto 0); vme_noga_i : in std_logic_vector(4 downto 0);
vme_use_ga_i : in std_logic; vme_use_ga_i : in std_logic;
afpga_clk_p_i : in std_logic;
afpga_clk_i : in std_logic; afpga_clk_n_i : in std_logic;
afpga_rst_n_i : in std_logic;
afpga_d_i : in std_logic_vector(7 downto 0); afpga_rx_i : in std_logic_vector(4 downto 0);
afpga_d_o : out std_logic_vector(7 downto 0); afpga_tx_o : out std_logic_vector(4 downto 0);
afpga_frame_i : in std_logic;
afpga_frame_o : out std_logic;
------------------------------------------------------------------------- -------------------------------------------------------------------------
-- AFPGA boot signals -- AFPGA boot signals
...@@ -261,7 +258,20 @@ architecture rtl of svec7_sfpga_top is ...@@ -261,7 +258,20 @@ architecture rtl of svec7_sfpga_top is
signal r_int_vector : std_logic_vector(7 downto 0); signal r_int_vector : std_logic_vector(7 downto 0);
signal r_irq_pending : std_logic; signal r_irq_pending : std_logic;
signal r_irq_ack : std_logic; signal r_irq_ack : std_logic;
signal afpga_clk_0 : std_logic;
signal afpga_clk_180 : std_logic;
signal pllout_clk_fb_afpga : std_logic;
signal pllout_clk_afpga_0 : std_logic;
signal pllout_clk_afpga_180 : std_logic;
signal afpga_dout : std_logic_vector(15 downto 0);
signal afpga_din : std_logic_vector(15 downto 0);
signal afpga_frame_out : std_logic;
signal afpga_frame_in : std_logic;
signal clk_bridge : std_logic;
signal rst_n_bridge : std_logic;
begin begin
-- PLL for producing 83.3 MHz system clock (clk_sys) from a 20 MHz reference. -- PLL for producing 83.3 MHz system clock (clk_sys) from a 20 MHz reference.
...@@ -297,10 +307,7 @@ begin ...@@ -297,10 +307,7 @@ begin
CLKFBIN => pllout_clk_fb_sys, CLKFBIN => pllout_clk_fb_sys,
CLKIN => lclk_i); CLKIN => lclk_i);
U_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
U_Powerup_Reset : reset_gen U_Powerup_Reset : reset_gen
port map ( port map (
...@@ -347,18 +354,43 @@ begin ...@@ -347,18 +354,43 @@ begin
-- trig2(27) <= vme_idle; -- trig2(27) <= vme_idle;
-- trig2(28) <= rst_n_sys; -- trig2(28) <= rst_n_sys;
xvme64x_bridge_serdes_1: entity work.xvme64x_bridge_serdes
generic map (
g_mode => MASTER,
g_platform => "spartan6")
port map (
rst_n_i => rst_n_i,
bridge_clk_o => clk_bridge,
bridge_rst_n_o => rst_n_bridge,
bridge_d_i => afpga_dout,
bridge_frame_i => afpga_frame_out,
bridge_d_o => afpga_din,
bridge_frame_o => afpga_frame_in,
ser_clk_p_i => afpga_clk_p_i,
ser_clk_n_i => afpga_clk_n_i,
ser_tx_o => afpga_tx_o,
ser_rx_i => afpga_rx_i);
xvme64x_core_master_1: entity work.xvme64x_core_master xvme64x_core_master_1: entity work.xvme64x_core_master
generic map ( generic map (
g_CLOCK_PERIOD => 8) g_CLOCK_PERIOD => 8)
port map ( port map (
afpga_clk_i => afpga_clk_i, afpga_clk_i => clk_bridge,
afpga_rst_n_i => afpga_rst_n_i, afpga_rst_n_i => rst_n_bridge,
vme_i => vme_in, vme_i => vme_in,
vme_o => vme_out_bridge, vme_o => vme_out_bridge,
afpga_d_i => afpga_d_i, afpga_d_i => afpga_din,
afpga_frame_i => afpga_frame_i, afpga_frame_i => afpga_frame_in,
afpga_d_o => afpga_d_o, afpga_d_o => afpga_dout,
afpga_frame_o => afpga_frame_o); afpga_frame_o => afpga_frame_out);
vme_ga <= vme_gap_i & vme_ga_i; vme_ga <= vme_gap_i & vme_ga_i;
......
hdl/top/svec7_test/svec7_test_top.vhd
View file @ 37d6449f
...@@ -80,14 +80,12 @@ entity svec7_test_top is ...@@ -80,14 +80,12 @@ entity svec7_test_top is
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
vme_sysreset_n_i : in std_logic; vme_sysreset_n_i : in std_logic;
sfpga_clk_o : out std_logic; sfpga_clk_p_o : out std_logic;
sfpga_rst_n_o : out std_logic; sfpga_clk_n_o : out std_logic;
sfpga_frame_o : out std_logic; sfpga_rx_i : in std_logic_vector(4 downto 0);
sfpga_d_o : out std_logic_vector(7 downto 0); sfpga_tx_o : out std_logic_vector(4 downto 0);
sfpga_frame_i : in std_logic := '0';
sfpga_d_i : in std_logic_vector(7 downto 0) := x"00";
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- SPI interfaces to DACs -- SPI interfaces to DACs
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -474,12 +472,10 @@ begin -- architecture arch ...@@ -474,12 +472,10 @@ begin -- architecture arch
pps_ext_i => pps_ext_in, pps_ext_i => pps_ext_in,
vme_sysreset_n_i => vme_sysreset_n_i, vme_sysreset_n_i => vme_sysreset_n_i,
sfpga_frame_i => sfpga_frame_i, sfpga_rx_i => sfpga_rx_i,
sfpga_frame_o => sfpga_frame_o, sfpga_tx_o => sfpga_tx_o,
sfpga_d_i => sfpga_d_i, sfpga_clk_p_o => sfpga_clk_p_o,
sfpga_d_o => sfpga_d_o, sfpga_clk_n_o => sfpga_clk_n_o,
sfpga_clk_o => sfpga_clk_o,
sfpga_rst_n_o => sfpga_rst_n_o,
fmc0_scl_b => fmc0_scl_b, fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b, fmc0_sda_b => fmc0_sda_b,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment