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Simple VME FMC Carrier SVEC
Commit 29b98259 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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bridge testing

parent 90348ce2
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.gitmodules
View file @ 29b98259
......@@ -4,3 +4,6 @@
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = https://ohwr.org/project/vme64x-core.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git
general-cores @ 90b33ae3
Subproject commit 5dde6da558083312cfd98d721e14b36a03e2a0bc
Subproject commit 90b33ae38bd152f9e4f665602e4e033f47f221b4
vme64x-core @ 6f359655
Subproject commit 1204aeca29ec3c72b6fa615976f000c664c7d152
Subproject commit 6f359655ae8e9f1cab3f85d673f430b80692ed7b
wr-cores @ 4482c478
Subproject commit 4482c478f29185f81dd45312f4f1ae2f28494957
hdl/rtl/bootloader/mini_vme.vhd
View file @ 29b98259
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2012-01-20
-- Last update: 2014-01-13
-- Last update: 2019-11-22
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -42,6 +42,7 @@ use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.VME64x_pkg.all;
entity xmini_vme is
generic (
......@@ -52,27 +53,9 @@ entity xmini_vme is
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Stripped-down VME bus.
VME_RST_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_LWORD_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0);
-- Geographical Address. Bit 5 is GA parity.
VME_GA_i : in std_logic_vector(5 downto 0);
VME_AM_i : in std_logic_vector(5 downto 0);
VME_ADDR_i : in std_logic_vector(31 downto 1);
-- Bidirectional/tristate driver signals: please put the tristates in the
-- top level entity of your design.
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
vme_i : in t_vme64x_in;
vme_o : out t_vme64x_out;
-- Wishbone master
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
......@@ -116,11 +99,11 @@ begin -- rtl
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
data_i => VME_AS_n_i,
data_i => VME_i.as_n,
npulse_o => as_p1,
synced_o => as_synced);
ds_a <= VME_DS_n_i(0) and VME_DS_n_i(1);
ds_a <= VME_i.ds_n(0) and VME_i.ds_n(1);
U_Sync_DS : gc_sync_ffs
port map (
......@@ -134,7 +117,7 @@ begin -- rtl
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
data_i => VME_WRITE_n_i,
data_i => VME_i.write_n,
synced_o => write_n);
......@@ -146,11 +129,11 @@ begin -- rtl
if(rst_n_i = '0') then
addr_valid <= '0';
elsif(as_p1 = '1') then
addr_latched <= VME_ADDR_i;
addr_latched <= VME_i.ADDR;
addr_valid <= '1';
am_latched <= VME_AM_i;
ga_latched <= VME_GA_i;
lword_latched <= VME_LWORD_n_i;
am_latched <= VME_i.AM;
ga_latched <= VME_i.GA;
lword_latched <= VME_i.LWORD_n;
elsif(as_synced = '1') then
addr_valid <= '0';
end if;
......@@ -163,8 +146,8 @@ begin -- rtl
if rst_n_i = '0' then
data_valid <= '0';
elsif(ds_p1 = '1') then
data_latched <= VME_DATA_b_i;
ds_latched <= VME_DS_n_i;
data_latched <= VME_i.DATA;
ds_latched <= vme_i.ds_n;
data_valid <= '1';
elsif(ds_synced = '1') then
data_valid <= '0';
......@@ -211,17 +194,17 @@ begin -- rtl
if rst_n_i = '0' then
state <= IDLE;
idle_o <= '1';
VME_DATA_DIR_o <= '0';
VME_DATA_OE_N_o <= '0';
VME_DTACK_n_o <= '0';
VME_DTACK_OE_o <= '0';
VME_o.DATA_DIR <= '0';
VME_o.DATA_OE_N <= '0';
VME_o.DTACK_n <= '0';
VME_o.DTACK_OE <= '0';
else
case state is
when IDLE =>
idle_o <= '1';
VME_DATA_DIR_o <= '0';
VME_DTACK_n_o <= '1';
VME_DTACK_OE_o <= '0';
VME_o.DATA_DIR <= '0';
VME_o.DTACK_n <= '1';
VME_o.DTACK_OE <= '0';
dtack_counter <= (others => '0');
if(addr_valid = '1' and data_valid = '1') then
......@@ -265,11 +248,11 @@ begin -- rtl
end if;
when DTACK =>
VME_DATA_b_o <= readback_data;
VME_o.DATA <= readback_data;
VME_DTACK_n_o <= '0';
VME_DTACK_OE_o <= '1';
VME_DATA_DIR_o <= not is_write;
VME_o.DTACK_n <= '0';
VME_o.DTACK_OE <= '1';
VME_o.DATA_DIR <= not is_write;
dtack_counter <= dtack_counter + 1;
......
hdl/rtl/bootloader/sfpga_bootloader.vhd
View file @ 29b98259
......@@ -400,7 +400,7 @@ begin -- behavioral
wb_out.err <= '0';
wb_out.rty <= '0';
wb_out.stall <= '0';
wb_out.int <= '0';
-- wb_out.int <= '0';
regs_out <= regs_out_local or regs_out_flash;
U_WB_SLAVE : svec_xloader_wb
......
hdl/rtl/svec7a/Manifest.py 0 → 100644
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files = [
"../svec_base_regs.vhd",
"svec7_base_wr.vhd",
"litedram_core.v"
]
hdl/rtl/svec7a/svec7_base_wr.vhd 0 → 100644
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hdl/sim/vme64x_bfm/vme64x_bfm.svh
View file @ 29b98259
......@@ -8,6 +8,7 @@
`define assert_wait(name, condition, timeout) \
begin\
time t=$time;\
$display("Cond: %b", condition);\
while(!(condition)) begin\
#1ns;\
if($time - t > timeout) begin\
......@@ -19,9 +20,6 @@ begin\
end
interface IVME64X ( input sys_rst_n_i );
wire as_n;
......
hdl/syn/svec7_test/Manifest.py
View file @ 29b98259
target = "xilinx"
action = "synthesis"
syn_device = "xc7k325t"
syn_grade = "-2"
syn_package = "ffg900"
syn_device = "xc7a200t"
syn_grade = "-3"
syn_package = "ffg1156"
syn_top = "svec7_test_top"
syn_project = "svec7_test_top"
syn_tool = "vivado"
board = "svec7a"
include_dirs=[ "../../../../vme64x-core/hdl/sim/vme64x_bfm",
"../../../../general-cores/sim",
"../../../../general-cores/modules/wishbone/wb_spi",
"../../../../general-cores/modules/wishbone/wb_lm32/src",
"." ]
files = [ "../../platform/xilinx/artix7/vivado/svec7_ip/svec7_ip.srcs/sources_1/ip/svec7_ddr3_controller/svec7_ddr3_controller.xci", "buildinfo_pkg.vhd" ]
modules = {
"local" : [ "../../rtl/svec7",
"local" : [ "../../rtl/svec7a",
"../../top/svec7_test",
"../../../../wr-cores",
"../../../../general-cores",
"../../../../vme64x-core"
"../../ip_cores/wr-cores",
"../../ip_cores/general-cores",
"../../ip_cores/vme64x-core",
],
}
try:
exec(open("../../ip_cores/general-cores/tools/gen_buildinfo.py").read())
except:
pass
hdl/syn/svec7_test/pins.xdc deleted 100644 → 0
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hdl/syn/svec7_test/svec7_pins.py deleted 100755 → 0
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hdl/syn/svec7_test/xc7k160tfbg676pkg.txt deleted 100644 → 0
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hdl/syn/svec7_test/xc7k325tffg900pkg.txt deleted 100644 → 0
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hdl/testbench/svec7_bridge/Manifest.py 0 → 100644
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action = "simulation"
target = "xilinx"
sim_tool = "modelsim"
sim_top = "main"
vcom_opt = "-93 -mixedsvvh"
syn_device = "xc7k325t"
svec_template_ucf = []
board = "svec7a"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
include_dirs=[ "../../ip_cores/vme64x-core/hdl/sim/vme64x_bfm",
"../../ip_cores/general-cores/sim",
"../../ip_cores/general-cores/modules/wishbone/wb_spi",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6",
"." ]
files = [ "main.sv", "buildinfo_pkg.vhd" ]
modules = {
"local" : [ "../../rtl/svec7a",
"../../top/svec7_sfpga",
"../../top/svec7_test",
"../../ip_cores/wr-cores",
"../../ip_cores/general-cores",
"../../ip_cores/vme64x-core"
],
}
# Do not fail during hdlmake fetch
try:
exec(open("../../ip_cores/general-cores/tools/gen_buildinfo.py").read())
except:
pass
hdl/testbench/svec7_bridge/buildinfo_pkg.vhd 0 → 100644
View file @ 29b98259
-- Buildinfo for project main
--
-- This file was automatically generated; do not edit
package buildinfo_pkg is
constant buildinfo : string :=
"buildinfo:1" & LF
& "module:main" & LF
& "commit:90348ce26bfdc3ee9b9477c26c91f74450f730db" & LF
& "syntool:modelsim" & LF
& "syndate:2019-11-27, 17:39 CET" & LF
& "synauth:Tomasz Wlostowski" & LF;
end buildinfo_pkg;
hdl/testbench/svec7_bridge/main.sv 0 → 100644
View file @ 29b98259
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
import wishbone_pkg::*;
module main;
reg rst_n = 0;
reg clk_125m_pllref = 0;
wire clk_62m5;
wire rst_62m5_n;
reg clk_local = 0;
always #25ns clk_local <= ~clk_local;
initial begin
repeat(20) @(posedge clk_125m_pllref);
rst_n = 1;
end
// 125Mhz
always #4ns clk_125m_pllref <= ~clk_125m_pllref;
IVME64X VME(rst_n);
`DECLARE_VME_BUFFERS(VME.slave);
logic ddr_reset_n;
logic ddr_ck_p;
logic ddr_ck_n;
logic ddr_cke;
logic ddr_ras_n;
logic ddr_cas_n;
logic ddr_we_n;
wire [7:0] ddr_dm;
logic [2:0] ddr_ba;
logic [14:0] ddr_a;
wire [63:0] ddr_dq;
wire [7:0] ddr_dqs_p;
wire [7:0] ddr_dqs_n;
wire ddr_rzq;
logic ddr_odt;
logic [4:0] slot_id = 5'h8;
wire [7:0] afpga_dout, afpga_din;
wire afpga_fout, afpga_fin ;
reg [7:0] afpga_dout_delayed, afpga_din_delayed;
reg afpga_fout_delayed, afpga_fin_delayed ;
wire afpga_clk, afpga_rst_n;
always@(afpga_dout)
#1ns afpga_dout_delayed <= afpga_dout;
always@(afpga_din)
#1ns afpga_din_delayed <= afpga_din;
always@(afpga_fout)
#1ns afpga_fout_delayed <= afpga_fout;
always@(afpga_fin)
#1ns afpga_fin_delayed <= afpga_fin;
svec7_sfpga_top
#(
.g_SIMULATION(1'b1)
)
DUT (
.rst_n_i(rst_n),
.lclk_i (clk_local),
.afpga_clk_i(afpga_clk),
.afpga_rst_n_i(afpga_rst_n),
.afpga_d_i(afpga_dout_delayed),
.afpga_d_o(afpga_din ),
.afpga_frame_o(afpga_fin),
.afpga_frame_i(afpga_fout_delayed),
.vme_as_n_i (VME_AS_n),
.vme_sysreset_n_i (VME_RST_n),
.vme_write_n_i (VME_WRITE_n),
.vme_am_i (VME_AM),
.vme_ds_n_i (VME_DS_n),
.vme_gap_i (^slot_id),
.vme_ga_i (~slot_id),
.vme_berr_o (VME_BERR),
.vme_dtack_n_o (VME_DTACK_n),
.vme_retry_n_o (VME_RETRY_n),
.vme_retry_oe_o (VME_RETRY_OE),
.vme_lword_n_b (VME_LWORD_n),
.vme_addr_b (VME_ADDR),
.vme_data_b (VME_DATA),
.vme_irq_o (VME_IRQ_n),
.vme_iack_n_i (VME_IACK_n),
.vme_iackin_n_i (VME_IACKIN_n),
.vme_iackout_n_o (VME_IACKOUT_n),
.vme_dtack_oe_o (VME_DTACK_OE),
.vme_data_dir_o (VME_DATA_DIR),
.vme_data_oe_n_o (VME_DATA_OE_N),
.vme_addr_dir_o (VME_ADDR_DIR),
.vme_addr_oe_n_o (VME_ADDR_OE_N)
);
svec7_test_top
#(
.g_SIMULATION(1'b1)
)
DUT2(
.rst_n_i(rst_n),
.clk_125m_pllref_p_i (clk_125m_pllref),
.clk_125m_pllref_n_i (~clk_125m_pllref),
.clk_20m_vcxo_i (clk_local),
.clk_125m_gtp_n_i (clk_125m_pllref),
.clk_125m_gtp_p_i (~clk_125m_pllref),
.sfpga_clk_o(afpga_clk),
.sfpga_rst_n_o(afpga_rst_n),
.sfpga_d_i(afpga_din_delayed ),
.sfpga_d_o(afpga_dout),
.sfpga_frame_o(afpga_fout),
.sfpga_frame_i(afpga_fin_delayed ),
.vme_sysreset_n_i(VME_RST_n),
.fmc0_scl_b (),
.fmc0_sda_b (),
.fmc1_scl_b (),
.fmc1_sda_b (),
.fmc0_prsnt_m2c_n_i (),
.fmc1_prsnt_m2c_n_i (),
.onewire_b (),
.carrier_scl_b (),
.carrier_sda_b (),
// .spi_sclk_o (),
.spi_ncs_o (),
.spi_mosi_o (),
.spi_miso_i (),
.uart_rxd_i (),
.uart_txd_o (),
.pll20dac_din_o (),
.pll20dac_sclk_o (),
.pll20dac_sync_n_o (),
.pll25dac_din_o (),
.pll25dac_sclk_o (),
.pll25dac_sync_n_o (),
.sfp_txp_o (),
.sfp_txn_o (),
.sfp_rxp_i (),
.sfp_rxn_i (),
.sfp_mod_def0_i (),
.sfp_mod_def1_b (),
.sfp_mod_def2_b (),
.sfp_rate_select_o (),
.sfp_tx_fault_i (),
.sfp_tx_disable_o (),
.sfp_los_i (),
.pcbrev_i (5'h2)
);
task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
uint64_t rv;
/* map func0 to 0x80000000, A32 */
acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
acc.read( 'h7ff63, rv, CR_CSR|A32|D08Byte3);
$display("Rv %x", rv );
acc.set_default_modifiers(A32 | D32 | SINGLE);
endtask // init_vme64x_core
initial begin
uint64_t d;
int i, result;
automatic CBusAccessor_VME64x acc = new(VME.tb);
// automatic CWishboneAccessor ddr4_acc = xwb_ddr4.get_accessor();
#5us;
init_vme64x_core(acc);
// Display meta data
d = 'hdeadbeef;
acc.write('h80000000, d, A32|SINGLE|D32);
d = 'hcafebabe;
acc.write('h80000004, d, A32|SINGLE|D32);
acc.read('h80000000, d, A32|SINGLE|D32);
$display("Rdbk[0] = %x", d);
acc.read('h80000004, d, A32|SINGLE|D32);
$display("Rdbk[4] = %x", d);
//$display("ddr status: %x", d);
end
endmodule // main
hdl/testbench/svec7_bridge/run.do 0 → 100644
View file @ 29b98259
vsim -quiet -L unisim work.main -novopt
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
do wave.do
run 10us
wave zoomfull
hdl/testbench/svec7_bridge/wave.do 0 → 100644
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This diff is collapsed.
hdl/testbench/svec7_test_top/Manifest.py
View file @ 29b98259
......@@ -6,33 +6,34 @@ vcom_opt = "-93 -mixedsvvh"
syn_device = "xc7k325t"
svec_template_ucf = []
board = "svec7"
board = "svec7a"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
include_dirs=[ "../../../../vme64x-core/hdl/sim/vme64x_bfm",
"../../../../general-cores/sim",
"../../../../general-cores/modules/wishbone/wb_spi",
"../../../../general-cores/modules/wishbone/wb_lm32/src",
include_dirs=[ "../../ip_cores/vme64x-core/hdl/sim/vme64x_bfm",
"../../ip_cores/general-cores/sim",
"../../ip_cores/general-cores/modules/wishbone/wb_spi",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6",
"." ]
files = [ "main.sv", "buildinfo_pkg.vhd" ]
modules = {
"local" : [ "../../rtl/svec7",
"local" : [ "../../rtl/svec7a",
"../../top/svec7_test",
"../../../../wr-cores",
"../../../../general-cores",
"../../../../vme64x-core"
"../../ip_cores/wr-cores",
"../../ip_cores/general-cores",
"../../ip_cores/vme64x-core"
],
}
# Do not fail during hdlmake fetch
try:
exec(open("../../../../general-cores/tools/gen_buildinfo.py").read())
exec(open("../../ip_cores/general-cores/tools/gen_buildinfo.py").read())
except:
pass
hdl/testbench/svec7_test_top/main.sv
View file @ 29b98259
......@@ -46,12 +46,12 @@ module main;
DUT (
.rst_n_i(rst_n),
.clk_62m5_pllref_p_i (clk_125m_pllref),
.clk_62m5_pllref_n_i (~clk_125m_pllref),
.clk_125m_pllref_p_i (clk_125m_pllref),
.clk_125m_pllref_n_i (~clk_125m_pllref),
.clk_20m_vcxo_i (1'b0),
.clk_125m_gtx_n_i (1'b0),
.clk_125m_gtx_p_i (1'b1),
.clk_125m_gtp_n_i (1'b0),
.clk_125m_gtp_p_i (1'b1),
.vme_as_n_i (VME_AS_n),
......
hdl/top/sfpga_bootloader/svec_sfpga_bridge.vhd 0 → 100644
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hdl/top/sfpga_bootloader/svec_sfpga_top.vhd
View file @ 29b98259
......@@ -113,6 +113,12 @@ entity svec_sfpga_top is
afpga_flash_cs_n_i : in std_logic;
afpga_flash_miso_o : out std_logic;
afpga_d_o : out std_logic_vector(7 downto 0);
afpga_frame_o : out std_logic;
afpga_d_i : in std_logic_vector(7 downto 0);
afpga_frame_i : in std_logic;
-- Onboard PLL enable signal. Must be one for the clock system to work.
pll_ce_o : out std_logic
......
hdl/top/svec7_sfpga/Manifest.py 0 → 100644
View file @ 29b98259
files = [ "svec7_sfpga_top.vhd", "svec7_sfpga_top.ucf", "reset_gen.vhd", "svec7_sfpga_bridge.vhd" ]
fetchto = "../../ip_cores"
modules = {
"local" : ["../../rtl/bootloader" ],
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git" ]
}
hdl/top/svec7_sfpga/reset_gen.vhd 0 → 100644
View file @ 29b98259
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity reset_gen is
port (
clk_sys_i : in std_logic;
rst_vme_n_a_i : in std_logic;
rst_local_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end reset_gen;
architecture behavioral of reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal local_synced_n : std_logic;
signal vme_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_vme_n_a_i,
synced_o => vme_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_local_n_a_i,
synced_o => local_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and local_synced_n and vme_synced_n;
end behavioral;
hdl/top/svec7_sfpga/svec7_sfpga_bridge.vhd 0 → 100644
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hdl/top/svec7_sfpga/svec7_sfpga_bridge2.vhd 0 → 100644
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hdl/top/svec7_sfpga/svec7_sfpga_top.ucf 0 → 100644
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hdl/top/svec7_sfpga/svec7_sfpga_top.vhd 0 → 100644
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hdl/top/svec7_test/svec7_test_top.vhd
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