Simple PCIe FMC carrier 7 (SPEC7)
Project description
The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an SFP connector. This board is optimised for cost and is usable with most of the FMC cards designed within the OHR project (e.g. ADC cards, Fine Delay).
The SPEC7 is the follow-up of the
SPEC of which the design
started in 2010 and for which certain components are obsolete.
Boards with a very similar architecture are available for the VME bus
(SVEC - Simple VME FMC Carrier
(SVEC)) and for the PXI
Express bus (SPEXI - Simple PXI express FMC Carrier Board
(SPEXI)).
Other FMC projects and the FMC standard are described in FMC
Projects.
Main Features - Under discussion
- Optmised for performance
- High-pin count FMC, better oscillators, lower jitter, more PCB layers, larger FPGA than those on SPEC
- SPEC was optimised for simplicity and cost
- Expected cost twice of SPEC
- 4-lane PCIe
- 1x Xilinx handling PCIe interface and user gateware
- FMC slot with high pin count (HPC) connector
- Not full HPC connectivity (not all high-speed serial lines)
- Vadj adjustable **
- Dedicated clock signals from Carrier to FMC (available on HPC pins) ?
- Clocking resources
- 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100 MHz (Silicon Labs Si570, freely usable)
- 1x 25 MHz TCXO with adjustable frequency (
AD5662, used by White Rabbit PTP core) - 1x 20 MHz VCXO with adjustable frequency (
AD5662, used by White Rabbit PTP core) - 1x low-jitter frequency synthesizer (
TI CDCM61004, fixed configuration, Fout=125 MHz, used by White Rabbit PTP core)
- On board memory
- 1x 2Gbit (256 MByte) DDR3 (?)
- 1x SPI flash PROM for multiboot FPGA powerup configuration, storage of the FPGA firmware or of critical data
- Miscellaneous
- on-board thermometer IC (DS18B20U+)
- unique 64-bit identifier (DS18B20U+)
- Front panel containing
- 1x Small Formfactor Pluggable (SFP) cage for fibre-optic transceiver (WhiteRabbit support). 1.25 and 2.5 Gbps.
- Programmable Red and Green LEDs
- FMC front panel
- Internal connectors
- 1x JTAG header for Xilinx programming during debugging
- 2x SATA connector
- 1x mini USB AB (USB-UART bridge)
- FPGA configuration. The FPGA can optionally be programmed from:
- JTAG header
- SPI Flash PROM
- Partial reprogramming via PCIe
- Stand-alone features
- External 12V power supply connector
- mini USB connector
- 4 LEDs
- 2 buttons
- Power consumption: 5-12 Watt, depending on application
- Optional cooling fan for the mezzanine.
Project information
- Official production documentation
- Users
- Frequently Asked Questions
Releases
Contacts
Commercial producers
General questions about project
- Erik van der Bij - CERN
Status
Date | Event |
10-01-2018 | Start working on project. Collecting main specifications. |
12-01-2018 | Main specifications collected. Discussion points documented. |
12 January 2018