Issues · Projects / Simple PCIe FMC carrier SPEC · Open Hardware Repository

V4 - Exposed pads IC5 and IC17 (TPS51200DRCT) not connected

#105 · opened Dec 09, 2019 by Erik van der Bij feature
- 0
updated Dec 09, 2019
V4 - SFP cage type is obsolete, EOL

#1 · opened Jan 25, 2018 by Erik van der Bij feature
- 0
updated Feb 12, 2019
Panel fiducials have offset

#2 · opened Jan 22, 2018 by Erik van der Bij feature
- 1
updated Nov 08, 2022
V4 - Package type D1,D2 wrongly mentioned in BOM. Partnumber OK.

#4 · opened Nov 08, 2017 by Erik van der Bij feature
- 1
updated Nov 09, 2022
V4 - front-panel drawing does not show licenced under CERN OHL.

#11 · opened May 29, 2017 by Erik van der Bij feature
- 0
updated Jan 19, 2023
V4 - Note on DAC output range wrong

#15 · opened Jul 23, 2015 by Erik van der Bij feature
- 2
updated Feb 15, 2019
V4 - consider adding a header with power and user-defined FPGA pins.

#18 · opened Sep 24, 2014 by Tomasz Wlostowski feature
- 0
updated Jul 24, 2023
PTS: timing violation in DAC signal.

#19 · opened Sep 22, 2014 by Erik van der Bij feature
- 0
updated Aug 24, 2023
V4 - consider placing fan instead of the cutout under FMC

#20 · opened Sep 19, 2014 by Tomasz Wlostowski feature
- 0
updated Oct 13, 2023
V4 - Make hardwired PLL settings configurable

#22 · opened Jul 24, 2014 by Erik van der Bij feature
- 0
updated Feb 12, 2019
V4 - Automatic 1x PCIe

#25 · opened Mar 21, 2014 by Projects feature
- 0
updated Feb 12, 2019
V4 - Manage T8 from P3V3_PCIE

#26 · opened Mar 21, 2014 by Projects feature
- 0
updated Feb 12, 2019
V4 - Reset timing of CDCM61004

#29 · opened Feb 07, 2014 by Tomasz Wlostowski feature
- 0
updated Feb 12, 2019
V4 - Consider adding connector to supply a fan

#31 · opened Jun 19, 2013 by Erik van der Bij feature
- 0
updated Feb 12, 2019
V4-0 - enlarge via size 450um to 550um

#32 · opened Jan 11, 2013 by Erik van der Bij feature
- 0
updated Feb 12, 2019
V4 - Add LED on FPGA DONE pin

#35 · opened Nov 01, 2012 by Projects feature
- 0
updated Feb 12, 2019
V4 - 3V3 regulator resistor values wrong

#36 · opened Sep 21, 2012 by Erik van der Bij feature
- 0
updated Feb 12, 2019
V4 - DDR3 pending End-of-life

#38 · opened Jul 10, 2012 by Erik van der Bij feature
- 1
updated Feb 12, 2019
V4 - Line impedances should be verified

#42 · opened May 23, 2012 by Erik van der Bij feature
- 3
updated Feb 12, 2019
V4 - Decoupling done different than Xilinx AN

#43 · opened May 23, 2012 by Erik van der Bij feature
- 0
updated Feb 12, 2019