A timing problem has been discovered in the PTS of the SVEC.
Likely this problem exists also in the PTS of the SPEC.
"The PTS test used for the SVEC/SPEC board changes DAC DIN signal at exactly the falling SCLK edge. Therefore, it violates the timing conditions indicated in the datasheet (setup time=5ns and hold time=4.5ns)"

Problem not urgent as the PTS basically only has to check if every solder connection is correctly done, even with the problem present, it will detect if the DAC would not be correctly connected.

See SPEC Feature #992 for details.