V4 - Make hardwired PLL settings configurable
For certain applications it would be good if the hardwired PLL parameters can be set differently. It is fixed to x5 (output 125 MHz). Some applications (e.g CERN BE/BI) may need other settings, like x4 (output 100 MHz).
This currently can be done by adding or removing some 0 Ohm resistors , but this needs hardware changes and may give problems with stock management.
It is suggested to make the PLL settings configurable under program
It would be nice if this could be backwards compatible (e.g. power-on setting the same as current design).
 Schematics page 2 top-right, resistors connected to IC6.
Q: Why not use the Si571 to make the 100 MHz?
A: Unfortunately the SI571 does not drive a GTP ref clk input. There is
a way to source the GTP ref clk via a GCLK net, but this does not work
well at 2.5Gbps due to the increased jitter. We were seeing ~1 PRBS
error per day when using the GCLK routing.
The only choice for the SFP GTP is to use the VCXO as the ref clk and to support our non standard 1.0Gbps and 2.0Gbps line rates from 125MHz is not possible.