V4 - Manage T8 from P3V3_PCIE
Comment from xavier serra:
If the 12V power comes from J6, the net USE_EXT_12V produces a short between P3V3_PCIE and P3V3. The short could produce a fight between the 3V3 supply from PCIe connector and the FPGA 3V3 supply, maybe the power supplies are protected against reverse voltatge (I haven't checked yet), but maybe is more interesting if the control of T8 MOSFET is managed from P3V3_PCIE net. If there is 3V3 volts in P3V3_PCIE, the T8 is open. If there is no 3V3 volts, T8 is closed(shorted) with the help of a pull down resitor on P3V3_PCIE net.
This issue has been raised when trying to use the SPEC board with miniPCIe (that doesn't supply 12V).