Commits · v2.0.1 · Projects / Simple PCIe FMC carrier SPEC

20 Aug, 2020 3 commits

Merge branch 'release/v2.0.1' into master · f63c5572
Federico Vaga authored Aug 20, 2020

f63c5572
update CHANGELOG for release · 55a623db
Federico Vaga authored Aug 20, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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55a623db

sw:drv: fix GN412x HW bug in FCL · 493405a4

Federico Vaga authored Aug 20, 2020

Programming cards in parallel does not work quite well. At best the
GN412x chip reports errors on all plugged cards. In other cases it
freezes the PC.

With this patch I am going to serialize the FCL access. Like this
cards will be programmed one after the other.

I do not know the origin of the bug, but it must be in the GN412x chip.
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

493405a4

30 Jul, 2020 7 commits
- Merge branch 'release/v2.0.0' into develop · 8970d3aa
  Federico Vaga authored Jul 30, 2020
  
  8970d3aa
- Merge branch 'release/v2.0.0' · f78d447e
  Federico Vaga authored Jul 30, 2020
  
  f78d447e
- apply internal guidelines for CHANGELOG · 1e9e50ec
  Federico Vaga authored Jul 30, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  1e9e50ec
- hdl|sw: update spec-base version for next release · 94bf3e4e
  Federico Vaga authored Jul 30, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  94bf3e4e
- update CHANGELOG for release · decbfd2d
  Federico Vaga authored Jul 30, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  decbfd2d
- bld: update CHANGELOG with hdl additions and modifications. · fcb30565
  Dimitris Lampridis authored Jul 30, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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  fcb30565
- Merge branch 'feature/hdl/top_level_cleanup' into develop · de80bdd9
  Dimitris Lampridis authored Jul 30, 2020
  
  de80bdd9
28 Jul, 2020 9 commits
- hdl: introduce golden-100T and golden-150T · 9288616d
  Dimitris Lampridis authored Jul 28, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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  9288616d
- hdl: remove golden_wr-150T, not used anymore. · a399b0fc
  Dimitris Lampridis authored Jul 28, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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  a399b0fc
- hdl: rename golden_wr top to spec_base_wr_example and clean-up. · 907cc696
  Dimitris Lampridis authored Jul 28, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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  907cc696
- hdl: rename dma_test testbench to golden. · 398dc356
  Dimitris Lampridis authored Jul 28, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
```
  398dc356
- hdl: rename golden to golden-45T. · cb256101
  Dimitris Lampridis authored Jul 28, 2020
  
  cb256101
- hdl: remove "full" top-level, not used anymore. · 659f3d8f
  Dimitris Lampridis authored Jul 28, 2020
```
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
```
  659f3d8f
- hdl: make dma_test testbench use the golden top-level. · bddf0f2c
  Dimitris Lampridis authored Jul 28, 2020
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Also remove the dma_test top-level, not used anymore.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
```
  bddf0f2c
- hdl: re-define and clean-up golden to also include DDR3. · 7051bce9
  Dimitris Lampridis authored Jul 28, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
```
  7051bce9
- hdl: add default value to app_wb_i port when not connected. · 13368245
  Dimitris Lampridis authored Jul 28, 2020
  
  13368245
27 Jul, 2020 3 commits
- Merge branch 'bugfix/dma_misalignment' into develop · 903f594d
  Dimitris Lampridis authored Jul 27, 2020
  
  903f594d
- hdl: fix DMA clock to 125MHz · f2dfe5de
  Dimitris Lampridis authored Jul 24, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
```
  f2dfe5de
- hdl: bump submodules to get latest releases · 682da324
  Dimitris Lampridis authored Jul 24, 2020
  
  682da324
24 Jul, 2020 4 commits
- hdl: Fix correct location for gen_sourceid.py script. · 15e93834
  Dimitris Lampridis authored Jul 13, 2020
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Depending on whether spec is a submodule of another project or a standalone project.
```
  15e93834
- hdl: introduce simplified top-level for DMA testing and update testbench · 8fbf7438
  Dimitris Lampridis authored Jun 29, 2020
  
  8fbf7438
- syn: constraints path correction · 90be31a5
  Evangelia Gousiou authored Jun 15, 2020
  
  90be31a5
- hdl: introduce DDR DMA testbench · 025c2a5d
  Dimitris Lampridis authored Jun 25, 2020
  
  025c2a5d
13 Jul, 2020 1 commit
- tst: fix skipif statement · 0ff34a6f
  Federico Vaga authored Jul 13, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  0ff34a6f
08 Jul, 2020 4 commits
- tst: remove unclear comment · 3564deba
  Federico Vaga authored Jul 08, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  3564deba
- sw: enforce scatterlist using a module parameter · a509cbd7
  Federico Vaga authored Jul 08, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  a509cbd7
- sw|doc: better explaination about the 4KiB write split · 6bf976cb
  Federico Vaga authored Jul 08, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  6bf976cb
- tst: make --bitstream optional · 3164b2c7
  Federico Vaga authored Jul 08, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  3164b2c7
06 Jul, 2020 5 commits
- sw: add tools to measure throughput · e5879288
  Federico Vaga authored Jul 06, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  e5879288
- tst: DMA read throughput test · 5545419e
  Federico Vaga authored Jul 06, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  5545419e
- sw:drv: add parameter to customize DMA allocation · 01547b49
  Federico Vaga authored Jul 06, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  01547b49
- sw:drv: accept the maximum DMA write length · 2a10539c
  Federico Vaga authored Jul 06, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  2a10539c
- sw:drv: delay DMA WRITE completion to overcome a bug · 3fdabb7a
  Federico Vaga authored Jul 06, 2020
```
The HDL asserts the IRQ line before the end of a write to DDR transfer.
We can't fix the problem on HDL due to lack of resources, so we add a
5us (empirical tests) delay in software.
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  3fdabb7a
02 Jul, 2020 4 commits
- doc: add DMA chapter · 32659261
  Federico Vaga authored Jul 02, 2020
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  32659261
- sw:drv: fix DMA size limitations · 7f6fb421
  Federico Vaga authored Jul 02, 2020
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No limites for read, but the implementation is not symmetric. For
DMA_MEM_TO_DEV the transfer size limitation is 4096.
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  7f6fb421
- fixup! tst: add regression test for 4Byte corruption · a6499126
  Federico Vaga authored Jul 02, 2020
  
  a6499126
- tst: program FPGA before running tests · 7f643fb0
  Federico Vaga authored Jul 02, 2020
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  7f643fb0