sw:drv: delay DMA WRITE completion to overcome a bug

The HDL asserts the IRQ line before the end of a write to DDR transfer. We can't fix the problem on HDL due to lack of resources, so we add a 5us (empirical tests) delay in software. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

sw:drv: delay DMA WRITE completion to overcome a bug
The HDL asserts the IRQ line before the end of a write to DDR transfer. We can't fix the problem on HDL due to lack of resources, so we add a 5us (empirical tests) delay in software. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
3fdabb7a · Federico Vaga · 32659261 · 3fdabb7a
Commit 3fdabb7a authored Jul 06, 2020 by Federico Vaga
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spec-gn412x-dma.c software/kernel/spec-gn412x-dma.c +9 -0

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--- a/software/kernel/spec-gn412x-dma.c
+++ b/software/kernel/spec-gn412x-dma.c
@@ -668,6 +668,15 @@ static irqreturn_t gn412x_dma_irq_handler(int irq, void *arg)
 	/* FIXME check for spurious - need HDL fix */
 	gn412x_dma_irq_ack(gn412x_dma);

+	if (unlikely(chan->sconfig.direction == DMA_MEM_TO_DEV)) {
+		/*
+		 * There is a bug in the HDL core, write path.
+		 * The IRQ line is asserted before the actual end of transfer.
+		 * A delay of 5us is the best compromise (empirical tests)
+		 */
+		ndelay(5000);
+	}
+
 	spin_lock_irqsave(&chan->lock, flags);
 	tx = chan->tx_curr;
 	chan->tx_curr = NULL;