Commit 3fdabb7a authored by Federico Vaga's avatar Federico Vaga

sw:drv: delay DMA WRITE completion to overcome a bug

The HDL asserts the IRQ line before the end of a write to DDR transfer.
We can't fix the problem on HDL due to lack of resources, so we add a
5us (empirical tests) delay in software.
Signed-off-by: Federico Vaga's avatarFederico Vaga <>
parent 32659261
......@@ -668,6 +668,15 @@ static irqreturn_t gn412x_dma_irq_handler(int irq, void *arg)
/* FIXME check for spurious - need HDL fix */
if (unlikely(chan->sconfig.direction == DMA_MEM_TO_DEV)) {
* There is a bug in the HDL core, write path.
* The IRQ line is asserted before the actual end of transfer.
* A delay of 5us is the best compromise (empirical tests)
spin_lock_irqsave(&chan->lock, flags);
tx = chan->tx_curr;
chan->tx_curr = NULL;
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