Commit f78d447e authored by Federico Vaga's avatar Federico Vaga

Merge branch 'release/v2.0.0'

parents 8c641a3b 1e9e50ec
......@@ -14,4 +14,5 @@ Module.symvers
GTAGS
GPATH
GRTAGS
Makefile.specific
\ No newline at end of file
Makefile.specific
compile_commands.json
..
SPDX-License-Identifier: CC-0.0
SPDX-FileCopyrightText: 2019 CERN
=========
Changelog
=========
[1.4.15] 2020-06-03
2.0.0 - 2020-07-30
==================
Added
-----
- hdl: new testbench to test the DMA feature (read/write to DDR memory) in the new golden.
- sw: basic Python module to handle DMA and FPGA programming
- sw: user-space DMA interface in debugfs (read/write)
- tst: add integration tests for DMA transfers
Changed
-------
- hdl: Switch to 125MHz (from 62.5MHz before) clock for DMA transfers.
- hdl: Cleanup of top-levels, addition of DMA to the golden.
Fixed
-----
- hdl: DMA misalignment issue due to loss of 32-bit words, caused in turn by inadequate flow control.
- hdl: typo in synthesis constraints.
1.4.15 - 2020-06-03
===================
Added
----
- [hdl] ignore autogenerated files to build metadata (otherwise the repository
-----
- hdl: ignore autogenerated files to build metadata (otherwise the repository
is always marked as dirty)
[1.4.14] 2020-05-28
1.4.14 - 2020-05-28
===================
Added
-----
- [hdl] export DDMTD clock output
- hdl: export DDMTD clock output
[1.4.13] 2020-05-12
1.4.13 - 2020-05-12
===================
Fixed
-----
- [hdl] report correct version in spec-base metadata
- hdl: report correct version in spec-base metadata
[1.4.12] 2020-05-12
1.4.12 - 2020-05-12
===================
Added
-----
- [hdl] metadata source-id automatic assignment
- hdl: metadata source-id automatic assignment
Changed
-----
- [sw] do not double remap memory
-------
- sw: do not double remap memory
[1.4.11] 2020-05-04
1.4.11 - 2020-05-04
===================
Added
-----
- [sw] added DMA engine channel for application to the list of resources
- sw: added DMA engine channel for application to the list of resources
Changed
-----
- [sw] little code improvements
-------
- sw: little code improvements
[1.4.10] 2020-04-24
1.4.10 - 2020-04-24
===================
Changed
-------
- [bld] assign dependencies path based on REPO_PARENT
- [bld] check for missing dependencies
- bld: assign dependencies path based on REPO_PARENT
- bld: check for missing dependencies
Fixed
-----
- [sw] fix kernel crash when programming new bitstream
- sw: fix kernel crash when programming new bitstream
[1.4.9] 2020-03-10
1.4.9 - 2020-03-10
==================
Added
-----
- [sw] support for kernel version more recent than 3.10 (RedHat)
- sw: support for kernel version more recent than 3.10 (RedHat)
Fixed
-----
- [sw] reduce allocation on stack
- sw: reduce allocation on stack
[1.4.8] 2020-02-12
1.4.8 - 2020-02-12
==================
Fixed
-----
- [sw] fix kernel crash when programming new bitstream
- sw: fix kernel crash when programming new bitstream
[1.4.7] 2020-01-15
1.4.7 - 2020-01-15
==================
Fixed
-------
- [doc] sysfs paths were wrong
- [doc] incomplete driver loading list of commands
- doc: sysfs paths were wrong
- doc: incomplete driver loading list of commands
[1.4.6] 2020-01-13
1.4.6 - 2020-01-13
==================
Changed
-------
- [doc] improve documentation
- [sw] better error reporting on I2C errors
- doc: improve documentation
- sw: better error reporting on I2C errors
[1.4.5] 2019-12-17
1.4.5 - 2019-12-17
==================
Something happened while synchronizing different branches and version 1.4.4
could be inconsistent on different repositories. This release increment realign
all repositories
[1.4.4] 2019-12-17
1.4.4 - 2019-12-17
==================
Changed
-----
- [sw] better integration in coht, rename environment variable to FPGA_MGR
-------
- sw: better integration in coht, rename environment variable to FPGA_MGR
Fixed
-----
- [sw] suggested fixed reported by checkpatch and coccicheck
- [hdl] restore lost references to git submodules
- sw: suggested fixed reported by checkpatch and coccicheck
- hdl: restore lost references to git submodules
[1.4.3] - 2019-10-17
====================
1.4.3 - 2019-10-17
==================
Fixed
-----
- [sw] fix SPEC GPIO get_direction
- sw: fix SPEC GPIO get_direction
[1.4.2] - 2019-10-15
====================
1.4.2 - 2019-10-15
==================
Fixed
-----
- [sw] fix SPEC driver dependency with I2C OCores
- sw: fix SPEC driver dependency with I2C OCores
[1.4.1] - 2019-09-23
====================
1.4.1 - 2019-09-23
==================
Changed
-------
- [sw] do not used devm_* operations (it seems to solve problems)
- sw: do not used devm_* operations (it seems to solve problems)
Removed
-------
- [sw] Removed IRQ line assignment to FCL (not used)
- sw: Removed IRQ line assignment to FCL (not used)
Fixed
-----
- [sw] kcalloc usage
- [sw] memcpy(), memset() usage
- [sw] checkpatch style fixes
- sw: kcalloc usage
- sw: memcpy(), memset() usage
- sw: checkpatch style fixes
[1.4.0] 2019-09-11
==================
1.4.0 2019-09-11
================
Added
-----
- [hdl] spec-base IP-core to support SPEC based designs
- [sw] Driver for GN4124 FCL using Linux FPGA manager
- [sw] Driver for GN4124 GPIO using Linux GPIOlib
- [sw] Driver for gn412x-core DMA using Linux DMA engine
- [sw] Support for spec-base IP-core
- [sw] Support for FMC
- hdl: spec-base IP-core to support SPEC based designs
- sw: Driver for GN4124 FCL using Linux FPGA manager
- sw: Driver for GN4124 GPIO using Linux GPIOlib
- sw: Driver for gn412x-core DMA using Linux DMA engine
- sw: Support for spec-base IP-core
- sw: Support for FMC
[0.0.0]
=======
0.0.0
=====
Start the development of a new SPEC driver and SPEC HDL support layer
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2. Waiver. To the greatest extent permitted by, but not in contravention
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partial invalidity or ineffectiveness shall not invalidate the remainder
of the License, and in such case Affirmer hereby affirms that he or she
will not (i) exercise any of his or her remaining Copyright and Related
Rights in the Work or (ii) assert any associated claims and causes of
action with respect to the Work, in either case contrary to Affirmer's
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4. Limitations and Disclaimers.
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surrendered, licensed or otherwise affected by this document.
b. Affirmer offers the Work as-is and makes no representations or
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c. Affirmer disclaims responsibility for clearing rights of other persons
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Further, Affirmer disclaims responsibility for obtaining any necessary
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......@@ -12,9 +12,9 @@
# add these directories to sys.path here. If the directory is relative to the
# documentation root, use os.path.abspath to make it absolute, like shown here.
#
# import os
# import sys
# sys.path.insert(0, os.path.abspath('.'))
import os
import sys
sys.path.insert(0, os.path.abspath('../software/PySPEC/PySPEC'))
# -- Project information -----------------------------------------------------
......@@ -39,7 +39,8 @@ release = 'v1.4'
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
# ones.
extensions = [
]
'sphinx.ext.autodoc'
]
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
......@@ -171,3 +172,7 @@ epub_title = project
# A list of files that should not be packed into the epub file.
epub_exclude_files = ['search.html']
autodoc_default_options = {
'member-order': 'bysource',
}
......@@ -27,6 +27,7 @@ You can clone the GIT project with the following command::
hdl-spec-base
sw-driver
sw-python
.. _`Open HardWare Repository`: https://ohwr.org/
.. _`SPEC project`: https://ohwr.org/project/spec
......@@ -34,7 +34,7 @@ GN4124 GPIO
GN4124 FCL
This driver provides support for the GN4124 FCL (FPGA Configuration Loader).
It uses the `FPGA manager interface`_ to program the FPGA at runtime.
It uses the `FPGA manager interface`_ to program the FPGA at run-time.
If the SPEC based application is using the :ref:`SPEC
base<spec_hdl_spec_base>` component then it can profit from the
......@@ -220,7 +220,7 @@ attributes. Here we focus only on those.
Miscellaneous information about the card status: IRQ mapping.
``<pci-id>/fpga_firmware`` [W]
It configure the FPGA with a bitstream which name is provided as input.
It configures the FPGA with a bitstream which name is provided as input.
Remember that firmwares are installed in ``/lib/firmware`` and alternatively
you can provide your own path by setting it in
``/sys/module/firmware_class/parameters/path``.
......@@ -231,3 +231,77 @@ attributes. Here we focus only on those.
``<pci-id>/spec-<pci-id>/build_info`` [R]
It shows the FPGA configuration synthesis information
``<pci-id>/spec-<pci-id>/dma`` [RW]
It exports DMA capabilities to user-space. The user can ``open(2)``
and ``close(2)`` to request and release a DMA engine channel. Then,
the user can use ``lseek(2)`` to set the offset in the DDR, and
``read(2)``/``write(2)`` to start the DMA transfer.
Module Parameters
-----------------
``user_dma_coherent_size`` [RW]
It sets the maximum size for a coherent DMA memory allocation. A
change to this value is applied on ``open(2)``
(file ``<pci-id>/spec-<pci-id>/dma``).
``user_dma_max_segment`` [RW]
It sets the maximum size for a DMA transfer in a scatterlist. A
change to this value is applied on the next ``read(2)`` or ``write(2)``
(file ``<pci-id>/spec-<pci-id>/dma``).
DMA
---
On SPEC-Based designs the DMA engine is implemented in HDL. This means
that you can't perform a DMA transfer without a *spec-base* device
on the FPGA.
The SPEC driver(s) implements the dmaengine API for the HDL DMA
engine. To request a dmaengine channel the user must provide a filter
function. The SPEC driver assigns to the application driver a
IORESOURCE_DMA which value is ``dma_device->dev_id << 16 |
channel_number``. Therefore, the user can use the following filter
function.::
static bool filter_function(struct dma_chan *dchan, void *arg)
{
struct dma_device *ddev = dchan->device;
int dev_id = (*((int *)arg) >> 16) & 0xFFFF;
int chan_id = *((int *)arg) & 0xFFFF;
return ddev->dev_id == dev_id && dchan->chan_id == chan_id;
}
void function(void)
{
struct resource *r;
int dma_dev_id;
dma_cap_mask_t dma_mask;
/* ... */
r = platform_get_resource(pdev, IORESOURCE_DMA, TDC_DMA);
dma_dev_id = r->start;
dma_cap_zero(dma_mask);
dma_cap_set(DMA_SLAVE, dma_mask);
dma_cap_set(DMA_PRIVATE, dma_mask);
dchan = dma_request_channel(dma_mask, filter_function,
dma_dev_id);
/* ... */
}
You can get the maximum transfer size by calling ``dma_get_max_seg_size()``.::
dma_get_max_seg_size(dchan->device->dev);
.. warning::
The GN4124 chip has a 4KiB payload. When doing a ``DMA_DEV_TO_MEM``
the HDL DMA engine splits transfers in 4KiB chunks, but for
``DMA_MEM_TO_DEV`` transfers the split should happen in the
driver: it does not happen. The DMA engine implementation
supports ``DMA_MEM_TO_DEV`` manly for testing purposes; to avoid
complications in the driver the 4KiB split is left to users.
..
SPDX-License-Identifier: CC-BY-SA-4.0
SPDX-FileCopyrightText: 2019-2020 CERN
.. _spec_python:
SPEC Python: PySPEC
===================
.. autoclass:: PySPEC.PySPEC
:members:
Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
Subproject commit 70f9de318f155764fdd4b7e1ae7f9c5b77131930
Subproject commit 56d855fc3d97c43e6f21ad669ecfda90971f0982
Subproject commit 258eb8e00f99f795fe9b98840b01ac4a8b92ec94
Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
Subproject commit e763762405dd5274d342285dbc64683221f1fb15
Subproject commit 25deb51759cf467df4fdeeca3bd10e4e793f71ca
Subproject commit a72a4223e2e1b521ba839f5623ee2857cf4fae10
......@@ -7,8 +7,14 @@ files = [
try:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec(open("../../../" + "/general-cores/tools/gen_sourceid.py").read(),
exec(open("../../../" + "general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'spec_base'})
except Exception as e:
print("Error: cannot generate source id file")
raise
try:
# Otherwise look for the local submodule of general-cores
exec(open("../ip_cores/" + "general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'spec_base'})
except Exception as e:
print("Error: cannot generate source id file")
raise
......@@ -301,7 +301,7 @@ entity spec_base_wr is
-- Addresses 0-0x1fff are not available (used by the carrier).
-- This is a pipelined wishbone with byte granularity.
app_wb_o : out t_wishbone_master_out;
app_wb_i : in t_wishbone_master_in;
app_wb_i : in t_wishbone_master_in := c_DUMMY_WB_MASTER_IN;
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
sim_wb_o : out t_wishbone_slave_out
......@@ -431,13 +431,7 @@ begin -- architecture top
g_WBM_TO_WB_FIFO_SIZE => 16,
g_WBM_TO_WB_FIFO_FULL_THRES => 12,
g_WBM_FROM_WB_FIFO_SIZE => 16,
g_WBM_FROM_WB_FIFO_FULL_THRES => 12,
g_P2L_FIFO_SIZE => 256,
g_P2L_FIFO_FULL_THRES => 175,
g_L2P_ADDR_FIFO_FULL_SIZE => 256,
g_L2P_ADDR_FIFO_FULL_THRES => 175,
g_L2P_DATA_FIFO_FULL_SIZE => 256,
g_L2P_DATA_FIFO_FULL_THRES => 175
g_WBM_FROM_WB_FIFO_FULL_THRES => 12
)
port map (
---------------------------------------------------------
......@@ -488,10 +482,10 @@ begin -- architecture top
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
wb_dma_cfg_clk_i => clk_62m5_sys,
wb_dma_cfg_clk_i => clk_62m5_sys,
wb_dma_cfg_rst_n_i => rst_62m5_sys_n,
wb_dma_cfg_i => dma_out,
wb_dma_cfg_o => dma_in,
wb_dma_cfg_i => dma_out,
wb_dma_cfg_o => dma_in,
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
......@@ -502,8 +496,8 @@ begin -- architecture top
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
wb_dma_dat_clk_i => clk_62m5_sys,
wb_dma_dat_rst_n_i => rst_gbl_n,
wb_dma_dat_clk_i => clk_125m_ref,
wb_dma_dat_rst_n_i => rst_125m_ref_n,
wb_dma_dat_o => gn_wb_ddr_out,
wb_dma_dat_i => gn_wb_ddr_in
);
......@@ -610,7 +604,7 @@ begin -- architecture top
metadata_data <= x"53504543";
when x"2" =>
-- Version
metadata_data <= x"0104000d";
metadata_data <= x"02000000";
when x"3" =>
-- BOM
metadata_data <= x"fffe0000";
......@@ -1110,8 +1104,8 @@ begin -- architecture top
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => rst_gbl_n,
wb1_clk_i => clk_62m5_sys,
wb1_rst_n_i => rst_125m_ref_n,
wb1_clk_i => clk_125m_ref,
wb1_sel_i => gn_wb_ddr_out.sel,
wb1_cyc_i => gn_wb_ddr_out.cyc,
wb1_stb_i => gn_wb_ddr_out.stb,
......
......@@ -114,7 +114,7 @@ NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk
# DMA
#---------------------------------------
NET "inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma.cmp_dma_controller/dma_async_*" TNM = FFS "dma_ffs";
NET "inst_spec_base/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma.cmp_dma_controller/dma_async_*" TNM = FFS "dma_ffs";
TIMESPEC TS_dma_async_ffs = FROM dma_ffs TO pci_clk 15ns DATAPATHONLY;
......
target = "xilinx"
action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_device = "xc6slx100t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden.xise"
syn_tool = "ise"
syn_top = "spec_golden"
syn_project = "spec_golden-100T.xise"
syn_tool = "ise"
syn_top = "spec_golden"
spec_base_ucf = ['onewire', 'spi', 'ddr3']
spec_base_ucf = ['onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
ctrls = ["bank3_32b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/golden", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"../../top/golden",
"../../syn/common",
],
}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
......
target = "xilinx"
action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden_wr.xise"
syn_tool = "ise"
syn_top = "spec_golden_wr"
syn_project = "spec_golden-150T.xise"
syn_tool = "ise"
syn_top = "spec_golden"
spec_base_ucf = ['onewire', 'spi', 'ddr3']
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
ctrls = ["bank3_32b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/golden_wr", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"../../top/golden",
"../../syn/common",
],
}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
......
target = "xilinx"
action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden_wr.xise"