- 29 Sep, 2020 3 commits
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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- 20 Aug, 2020 4 commits
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Federico Vaga authored
2.0.0 - 2020-08-20 ================== Fixed ----- - program 2 or more SPEC FPGAs in parallel. There is a bug in the GN412x chip that we fixed in software by serializing any attempt of parallel programming
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Programming cards in parallel does not work quite well. At best the GN412x chip reports errors on all plugged cards. In other cases it freezes the PC. With this patch I am going to serialize the FCL access. Like this cards will be programmed one after the other. I do not know the origin of the bug, but it must be in the GN412x chip. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 30 Jul, 2020 7 commits
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
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- 28 Jul, 2020 9 commits
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Also remove the dma_test top-level, not used anymore. Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
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- 27 Jul, 2020 3 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
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- 24 Jul, 2020 4 commits
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Dimitris Lampridis authored
Depending on whether spec is a submodule of another project or a standalone project.
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Dimitris Lampridis authored
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Evangelia Gousiou authored
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Dimitris Lampridis authored
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- 13 Jul, 2020 1 commit
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 08 Jul, 2020 4 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 06 Jul, 2020 5 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
The HDL asserts the IRQ line before the end of a write to DDR transfer. We can't fix the problem on HDL due to lack of resources, so we add a 5us (empirical tests) delay in software. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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