WIP: added 2 more rx status bits: one activated upon CTRL byte reception and one upon detection of more bytes than the max frame size

version in CHARM

Conflicts:
	.gitmodules
	ip_cores/general-cores
	ip_cores/gn4124-core
	ip_cores/wr-cores
	rtl/fmc_masterFIP_core.vhd
	rtl/fmc_masterFIP_mezz.vhd
	rtl/fmc_masterfip_csr.vhd
	rtl/masterFIP_pkg.vhd
	rtl/masterfip_rx.vhd
	rtl/masterfip_tx.vhd
	rtl/wbgen/fmc_masterfip_csr.wb
	sim/spec/data_vectors/masterFIP_test.vec
	sim/spec/testbench/tb_masterFIP.vhd
	syn/spec/spec_masterfip_mt.xise
	top/spec/spec_masterFIP.ucf
	top/spec/spec_masterFIP.vhd

added more bits to tx and rx bytes counters so as to be compatible with the PTS that needs to send 1024 bytes.

removed sw folder; changed general-cores branch (tom-proposed-master-feb28; unused IOBs set to floating; clean up counters

added all the submodules needed in ip_cores so that they are not taken from ip_cores/wr-node-core/hdl/ip-cores

direct access to the host is now given through the fmc0_host port of MT.

- cleaned up simulation

- general clean-up
- updated and renamed wbgen2 fileset.xml