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MasterFIP - Gateware
Commit 96af285b authored by Evangelia Gousiou's avatar Evangelia Gousiou
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WIP cleanup following review recommendations

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rtl/carrier_info.vhd deleted 100644 → 0
View file @ 68a9872f
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Misc Info about Carrier
---------------------------------------------------------------------------------------
-- File : carrier_info.vhd
-- Author : auto-generated by wbgen2 from carrier_info.wb
-- Created : 01/22/14 15:17:10
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_info.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity carrier_info is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
carrier_info_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
carrier_info_carrier_reserved_i : in std_logic_vector(11 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
carrier_info_carrier_type_i : in std_logic_vector(15 downto 0);
-- Port for BIT field: 'FMC presence' in reg: 'Status'
carrier_info_stat_fmc_pres_i : in std_logic;
-- Port for BIT field: 'GN4142 core P2L PLL status' in reg: 'Status'
carrier_info_stat_p2l_pll_lck_i : in std_logic;
-- Port for BIT field: 'System clock PLL status' in reg: 'Status'
carrier_info_stat_sys_pll_lck_i : in std_logic;
-- Port for BIT field: 'DDR3 calibration status' in reg: 'Status'
carrier_info_stat_ddr3_cal_done_i : in std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status'
carrier_info_stat_reserved_i : in std_logic_vector(27 downto 0);
-- Port for BIT field: 'Green LED' in reg: 'Control'
carrier_info_ctrl_led_green_o : out std_logic;
-- Port for BIT field: 'Red LED' in reg: 'Control'
carrier_info_ctrl_led_red_o : out std_logic;
-- Port for BIT field: 'DAC clear' in reg: 'Control'
carrier_info_ctrl_dac_clr_n_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
carrier_info_ctrl_reserved_o : out std_logic_vector(28 downto 0);
-- Ports for BIT field: 'State of the reset line' in reg: 'Reset Register'
carrier_info_rst_fmc0_n_o : out std_logic;
carrier_info_rst_fmc0_n_i : in std_logic;
carrier_info_rst_fmc0_n_load_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register'
carrier_info_rst_reserved_o : out std_logic_vector(30 downto 0)
);
end carrier_info;
architecture syn of carrier_info is
signal carrier_info_ctrl_led_green_int : std_logic ;
signal carrier_info_ctrl_led_red_int : std_logic ;
signal carrier_info_ctrl_dac_clr_n_int : std_logic ;
signal carrier_info_ctrl_reserved_int : std_logic_vector(28 downto 0);
signal carrier_info_rst_reserved_int : std_logic_vector(30 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_info_ctrl_led_green_int <= '0';
carrier_info_ctrl_led_red_int <= '0';
carrier_info_ctrl_dac_clr_n_int <= '0';
carrier_info_ctrl_reserved_int <= "00000000000000000000000000000";
carrier_info_rst_fmc0_n_load_o <= '0';
carrier_info_rst_reserved_int <= "0000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
carrier_info_rst_fmc0_n_load_o <= '0';
ack_in_progress <= '0';
else
carrier_info_rst_fmc0_n_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= carrier_info_carrier_pcb_rev_i;
rddata_reg(15 downto 4) <= carrier_info_carrier_reserved_i;
rddata_reg(31 downto 16) <= carrier_info_carrier_type_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= carrier_info_stat_fmc_pres_i;
rddata_reg(1) <= carrier_info_stat_p2l_pll_lck_i;
rddata_reg(2) <= carrier_info_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_info_stat_ddr3_cal_done_i;
rddata_reg(31 downto 4) <= carrier_info_stat_reserved_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
carrier_info_ctrl_led_green_int <= wrdata_reg(0);
carrier_info_ctrl_led_red_int <= wrdata_reg(1);
carrier_info_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_info_ctrl_reserved_int <= wrdata_reg(31 downto 3);
end if;
rddata_reg(0) <= carrier_info_ctrl_led_green_int;
rddata_reg(1) <= carrier_info_ctrl_led_red_int;
rddata_reg(2) <= carrier_info_ctrl_dac_clr_n_int;
rddata_reg(31 downto 3) <= carrier_info_ctrl_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_info_rst_fmc0_n_load_o <= '1';
carrier_info_rst_reserved_int <= wrdata_reg(31 downto 1);
end if;
rddata_reg(0) <= carrier_info_rst_fmc0_n_i;
rddata_reg(31 downto 1) <= carrier_info_rst_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- PCB revision
-- Reserved register
-- Carrier type
-- FMC presence
-- GN4142 core P2L PLL status
-- System clock PLL status
-- DDR3 calibration status
-- Reserved
-- Green LED
carrier_info_ctrl_led_green_o <= carrier_info_ctrl_led_green_int;
-- Red LED
carrier_info_ctrl_led_red_o <= carrier_info_ctrl_led_red_int;
-- DAC clear
carrier_info_ctrl_dac_clr_n_o <= carrier_info_ctrl_dac_clr_n_int;
-- Reserved
carrier_info_ctrl_reserved_o <= carrier_info_ctrl_reserved_int;
-- State of the reset line
carrier_info_rst_fmc0_n_o <= wrdata_reg(0);
-- Reserved
carrier_info_rst_reserved_o <= carrier_info_rst_reserved_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
rtl/fmc_masterFIP_core.vhd
View file @ 96af285b
......@@ -520,8 +520,9 @@ begin
else
if rx_frame_ok_p = '1' then
reg_to_mt.rx_stat_frame_ok_i <= rx_frame_ok_p;
reg_to_mt.rx_stat_bytes_num_i(C_FRAME_BYTES_CNT_LGTH-1 downto 0) <= rx_byte_index - 3; -- data payload, without FSS, CTRL,
end if; -- CRC, FES
reg_to_mt.rx_stat_bytes_num_i(C_FRAME_BYTES_CNT_LGTH-1 downto 0) <= rx_byte_index - 3;
-- data payload, without FSS, CTRL, CRC, FES
end if;
end if;
end if;
end process;
......@@ -576,14 +577,15 @@ begin
(clk_i => clk_i,
rst_i => tx_rst,
speed_i => speed,
tx_bytes_num_i => reg_from_mt.tx_ctrl_bytes_num_o(C_FRAME_BYTES_CNT_LGTH-1 downto 0),-- num of bytes to serialize; sampled upon tx_start_p
tx_start_p_i => reg_from_mt.tx_ctrl_start_o, -- monostable, 1-clk-tick-long pulse
tx_bytes_num_i => reg_from_mt.tx_ctrl_bytes_num_o(C_FRAME_BYTES_CNT_LGTH-1 downto 0),
-- num of bytes to serialize; sampled upon tx_start_p
tx_start_p_i => reg_from_mt.tx_ctrl_start_o, -- monostable, 1-clk-tick-long pulse
tx_frame_i => tx_frame,
tx_ctrl_byte_i => reg_from_mt.tx_payld_ctrl_o,
tx_byte_index_o => reg_to_mt.tx_stat_curr_byte_indx_i(C_FRAME_BYTES_CNT_LGTH-1 downto 0),
-- indx of current byte being serialized,
-- counting starts from 0 (indx 0 is
-- the Control byte) up to 262 bytes
-- indx of current byte being serialized,
-- counting starts from 0 (indx 0 is
-- the Control byte) up to 262 bytes
tx_end_p_o => tx_completed_p,
tx_d_o => fd_txd,
tx_ena_o => fd_txena,
......
rtl/leds_manager.vhd deleted 100644 → 0
View file @ 68a9872f
This diff is collapsed.
rtl/masterfip_rx.vhd
View file @ 96af285b
......@@ -164,25 +164,25 @@ end entity masterfip_rx;
architecture struc of masterfip_rx is
-- wf_rx_osc
signal s_rx_osc_rst, s_adjac_bits_window : std_logic;
signal s_signif_edge_window : std_logic;
signal s_sample_bit_p : std_logic;
signal s_sample_manch_bit_p : std_logic;
signal rx_osc_rst, adjac_bits_window : std_logic;
signal signif_edge_window : std_logic;
signal sample_bit_p : std_logic;
signal sample_manch_bit_p : std_logic;
-- wf_rx_deglitcher
signal s_fd_rxd_filt, s_rxd_filt_edge_p : std_logic;
signal s_fd_rxd_filt_f_edge_p : std_logic;
signal s_fd_rxd_filt_r_edge_p : std_logic;
signal fd_rxd_filt, rxd_filt_edge_p : std_logic;
signal fd_rxd_filt_f_edge_p : std_logic;
signal fd_rxd_filt_r_edge_p : std_logic;
-- wf_rx_deserializer
signal rx_byte_ready_p : std_logic;
signal rx_fss_crc_fes_ok_p : std_logic;
signal rx_byte : std_logic_vector (C_BYTE_WIDTH-1 downto 0);
signal rx_byte_ready_p : std_logic;
signal rx_fss_crc_fes_ok_p : std_logic;
signal rx_byte : std_logic_vector (C_BYTE_WIDTH-1 downto 0);
-- retrieved bytes into 32-bit regs
signal byte0, byte1, byte2, byte3 : std_logic_vector(C_BYTE_WIDTH-1 downto 0);
signal zero : std_logic_vector(C_BYTE_WIDTH-1 downto 0) := (others => '0');
signal word32_num : integer range 0 to C_MAX_FRAME_WORDS-1;
signal byte0, byte1, byte2, byte3 : std_logic_vector(C_BYTE_WIDTH-1 downto 0);
signal zero : std_logic_vector(C_BYTE_WIDTH-1 downto 0) := (others => '0');
signal word32_num : integer range 0 to C_MAX_FRAME_WORDS-1;
-- bytes counter
signal rx_byte_index, rx_byte_index_d1 : std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
signal bytes_c_rst : std_logic;
signal rx_byte_index, rx_byte_index_d1 : std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
signal bytes_c_rst : std_logic;
--=================================================================================================
......@@ -197,14 +197,14 @@ begin
cmp_rx_deglitcher: wf_rx_deglitcher
port map(
uclk_i => clk_i,
nfip_rst_i => rst_i, -- or rx_rst??
nfip_rst_i => rx_rst_i,
fd_rxd_a_i => rx_d_a_i,
-----------------------------------------------------------------
fd_rxd_filt_o => s_fd_rxd_filt,
fd_rxd_filt_edge_p_o => s_rxd_filt_edge_p,
fd_rxd_filt_f_edge_p_o => s_fd_rxd_filt_f_edge_p);
fd_rxd_filt_o => fd_rxd_filt,
fd_rxd_filt_edge_p_o => rxd_filt_edge_p,
fd_rxd_filt_f_edge_p_o => fd_rxd_filt_f_edge_p);
-----------------------------------------------------------------
s_fd_rxd_filt_r_edge_p <= s_rxd_filt_edge_p and (not s_fd_rxd_filt_f_edge_p);
fd_rxd_filt_r_edge_p <= rxd_filt_edge_p and (not fd_rxd_filt_f_edge_p);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_deserializer: wf_rx_deserializer
......@@ -212,18 +212,18 @@ begin
uclk_i => clk_i,
nfip_rst_i => rst_i,
rx_rst_i => rx_rst_i,
fd_rxd_f_edge_p_i => s_fd_rxd_filt_f_edge_p,
fd_rxd_r_edge_p_i => s_fd_rxd_filt_r_edge_p,
fd_rxd_i => s_fd_rxd_filt,
sample_bit_p_i => s_sample_bit_p,
sample_manch_bit_p_i => s_sample_manch_bit_p,
signif_edge_window_i => s_signif_edge_window,
adjac_bits_window_i => s_adjac_bits_window,
fd_rxd_f_edge_p_i => fd_rxd_filt_f_edge_p,
fd_rxd_r_edge_p_i => fd_rxd_filt_r_edge_p,
fd_rxd_i => fd_rxd_filt,
sample_bit_p_i => sample_bit_p,
sample_manch_bit_p_i => sample_manch_bit_p,
signif_edge_window_i => signif_edge_window,
adjac_bits_window_i => adjac_bits_window,
-----------------------------------------------------------------
byte_o => rx_byte,
byte_ready_p_o => rx_byte_ready_p,
fss_crc_fes_ok_p_o => rx_fss_crc_fes_ok_p,
rx_osc_rst_o => s_rx_osc_rst,
rx_osc_rst_o => rx_osc_rst,
fss_received_p_o => rx_fss_received_p_o,
crc_wrong_p_o => rx_crc_wrong_p_o);
-----------------------------------------------------------------
......@@ -237,13 +237,13 @@ begin
uclk_i => clk_i,
rate_i => speed_i, -- or rx_rst??
nfip_rst_i => rst_i,
fd_rxd_edge_p_i => s_rxd_filt_edge_p,
rx_osc_rst_i => s_rx_osc_rst,
fd_rxd_edge_p_i => rxd_filt_edge_p,
rx_osc_rst_i => rx_osc_rst,
-----------------------------------------------------------------
rx_manch_clk_p_o => s_sample_manch_bit_p,
rx_bit_clk_p_o => s_sample_bit_p,
rx_signif_edge_window_o => s_signif_edge_window,
rx_adjac_bits_window_o => s_adjac_bits_window);
rx_manch_clk_p_o => sample_manch_bit_p,
rx_bit_clk_p_o => sample_bit_p,
rx_signif_edge_window_o => signif_edge_window,
rx_adjac_bits_window_o => adjac_bits_window);
-----------------------------------------------------------------
......
rtl/masterfip_tx.vhd
View file @ 96af285b
......@@ -103,7 +103,15 @@ use work.wf_package.all;
-- Entity declaration for masterfip_tx
--=================================================================================================
entity masterfip_tx is port(
entity masterfip_tx is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
g_simul : boolean := FALSE); -- set to TRUE when instantiated in a test-bench
port(
-- INPUTS
clk_i : in std_logic; -- only one clk domain
......@@ -291,7 +299,7 @@ begin
prod_data_lgth_match <= '1' when prod_bytes_c = bytes_num else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
synch_signals: process (clk_i)
p_delay: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
......
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