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MasterFIP - Gateware
Commit 76d20a64 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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ext_sync_pulse_oe_n controlled by MT, not fixed to '0'

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rtl/fmc_masterFIP_core.vhd
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......@@ -40,7 +40,7 @@
-- Figure 1: fmc_masterFIP_core architecture |
-- |
-- MASTERFIP WBGEN2 CSR: |
-- The mrfip_wbgen2_csr module has been generated through the wbgen2 application. |
-- The masterfip_wbgen2_csr module has been generated through the wbgen2 application.|
-- It establishes the interface with the processor, usually a Mock Turtle core. |
-- This interface contains a set of control and status registers for each one of the |
-- units of Figure 1; it also contains the WorldFIP frame PAYLOAD data for the TX |
......@@ -56,7 +56,7 @@
-- The masterfip_tx places a complete WorldFIP frame on the WorldFIP bus. |
-- The masterfip_tx ignores the frame type (ID_DAT/RT_DAT/RP_MSG etc..), or the |
-- macrocycle sequence and macrocycle timing; the processor (MT) is responsible for |
-- managing all these issues and for providing to the masterfip_tx the bytes to |
-- managing all these aspects and for providing to the masterfip_tx the bytes to |
-- serialise, along with a start pulse. |
-- The communication between the processor and the masterfip_tx is handled through a |
-- set of control (from the MT) and status (from the masterfip_tx) signals/registers |
......@@ -78,7 +78,7 @@
-- |
-- MASTERFIP RX: |
-- The masterfip_rx retrieves a WorldFIP frame from the WorldFIP bus. |
-- Similarly to the masterfip_tx, the masterfip_rx has no intelligence regarding the |
-- Similar to the masterfip_tx, the masterfip_rx has no intelligence regarding the |
-- macrocycle sequence; it is controlled and monitored by the processor (MT) through |
-- the masterfip_wbgen2_csr, where a set of control and status registers are defined.|
-- As long as it is not under reset, the masterfip_rx is probing the WorldFIP bus |
......
syn/spec/spec_masterfip_mt.par
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syn/spec/spec_masterfip_mt.syr
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syn/spec/spec_masterfip_mt.twr
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syn/spec/spec_masterfip_mt_map.mrp
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top/spec/spec_masterfip_mt.vhd
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......@@ -31,7 +31,7 @@
-- |V| | | | . .|. .>| CPU0 | _____ | X | | G | | | |
-- |E| | | M | ____ . | |______| | | | b | | N | | | <-PCIe->|
-- |_| | | A | | | . | | SH. | | a | | 4 | | | host |
-- | | S |....|Xbar|... | ______ | MEM | | r | | 1 | | | |
-- | | S |. . |Xbar|. . | ______ | MEM | | r | | 1 | | | |
-- ext pulse --> | | T | |____| . | | | |_____| | | | 2 | | | |
-- | | E | . | DP | CPU1 | | | | 4 | | | |
-- | | R | . .|. .>|______| | | | | | | |
......@@ -191,7 +191,7 @@ entity spec_masterfip_mt is
tx_error_i : in std_logic; -- transmit error
vc_rdy_i : in std_logic_vector(1 downto 0); -- channel ready
-- DAC I2C (driven by MT for max stability on the 100 MHz clk)
-- DAC I2C (driven by MT to the VCXO mid range -fixed value- for max stability on the 100 MHz clk)
dac_cs_n_o : out std_logic_vector(1 downto 0); -- 0: select SPEC 25MHz OSC5 VCXO
dac_sclk_o : out std_logic; -- 1: select SPEC 20MHz OSC1 VCXO
dac_din_o : out std_logic;
......@@ -225,8 +225,8 @@ entity spec_masterfip_mt is
-- External synchronisation pulse (input signal and transceiver control)
ext_sync_term_en_o : out std_logic; -- enable 50 Ohm termin of the pulse
ext_sync_dir_o : out std_logic := '0'; -- direction fixed B -> A
ext_sync_oe_n_o : out std_logic := '0'; -- output fixed to enabled
ext_sync_i : in std_logic; -- sync pulse
ext_sync_oe_n_o : out std_logic; -- transceiver output enable
ext_sync_i : in std_logic; -- input sync pulse
-- FMC Front panel LEDs: controlled by the MT firmware, updated every macrocycle
led_rx_act_n_o : out std_logic;
......@@ -258,7 +258,7 @@ architecture rtl of spec_masterfip_mt is
-- MOCK TURTLE CONSTANTS --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- HMQ: It total 10 HMQs have been defined. Each HMQ has 4 entries of 128 x 32 bits, each.
-- HMQ: It total 10 HMQs have been defined. Each HMQ has 4 entries of 128 x 32 bits.
-- 8 "out HMQs" from the MT -> towards the host
-- - 0: HMQ from CPU0 with the WorldFIP payloads from periodic consumed variables
......@@ -271,7 +271,7 @@ architecture rtl of spec_masterfip_mt is
-- (aperiodic presence and identification)
-- - 5: HMQ for debugging data from CPU0 and CPU1 towards the host
-- - 6: HMQ for the responses of CPU0 to the commands of the host, see below "in HMQ0"
-- (e.g.: acknowledgement of the configuration???)
-- (acknowledgement of the configuration; load, start, stop, reset macrocycle)
-- - 7: HMQ for the responses of CPU1 to the commands of the host, see below "in HMQ1",
-- (e.g.: content of the report variable)
......@@ -354,7 +354,6 @@ begin
-- FIXED SIGNALS --
---------------------------------------------------------------------------------------------------
ext_sync_dir_o <= '0'; -- Direction fixed to: B -> A
ext_sync_oe_n_o <= '0'; -- Output fixed to: enabled
-- To be removed on hw V3
-- Note: For the hw v1 signals ext_sync_tst_n_o, adc_prim_conn_n_o and adc_sec_conn_n_o, in order
......@@ -485,7 +484,7 @@ begin
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_a_i => ext_sync_i,
ext_sync_dir_o => open, -- hard-wired to '0'
ext_sync_oe_n_o => open, -- hard-wired to '0'
ext_sync_oe_n_o => ext_sync_oe_n_o,
-- LEDs
leds_o => leds,
-- WISHBONE interface with MT CPU0 and CPU1
......
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