Commit 780492d1 authored by Evangelia Gousiou's avatar Evangelia Gousiou

used wbgen2 files with versioning regs; resynthesised

parent 96af285b
......@@ -105,9 +105,8 @@ use work.wf_package.all;
entity masterfip_tx is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
g_simul : boolean := FALSE); -- set to TRUE when instantiated in a test-bench
......
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......@@ -3,7 +3,8 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 04/21/17 11:57:29
-- Created : 06/30/17 10:03:28
-- Version : 0x00000001
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -210,6 +211,7 @@ package masterfip_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_masterfip_out_registers is record
ver_id_o : std_logic_vector(31 downto 0);
rst_core_o : std_logic;
rst_fd_o : std_logic;
led_rx_act_o : std_logic;
......@@ -306,6 +308,7 @@ package masterfip_wbgen2_pkg is
end record;
constant c_masterfip_out_registers_init_value: t_masterfip_out_registers := (
ver_id_o => (others => '0'),
rst_core_o => '0',
rst_fd_o => '0',
led_rx_act_o => '0',
......
......@@ -2,8 +2,8 @@ peripheral {
name = "FMC masterFIP core registers";
description = "Wishbone slave for FMC masterFIP core";
hdl_entity = "masterfip_wbgen2_csr";
prefix = "masterfip";
version = 1;
-- Note that for html readability, some of the lines are longer than 100 characters.
......@@ -18,7 +18,8 @@ peripheral {
field {
name = "reset of the masterFIP core";
description = "write 1: generates a 1-clk-tick-long (10ns) masterFIP core reset;\
note: there is no need to clear the bit before writing another '1'";
note: there is no need to clear the bit before writing another '1';\
it s also not meaningful to read back this register";
type = MONOSTABLE;
prefix = "core";
};
......@@ -27,7 +28,8 @@ peripheral {
name = "reset of the FielDrive chip";
description = "write 1: to generate a FielDrive reset;\
upon writing, the fmc_masterFIP_core generates a 1-WorldFIP-clk-tick-long FD RSTN;\
note: there is no need to clear the bit before writing another '1'";
note: there is no need to clear the bit before writing another '1';\
it s also not meaningful to read back this register";
type = MONOSTABLE;
prefix = "fd";
};
......
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......@@ -871,10 +871,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
......
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