Commit d062b959 authored by Evangelia Gousiou's avatar Evangelia Gousiou

cleanup

parent 9840fca3
......@@ -812,7 +812,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- registering of the read values upon the activation of the id_read_o
reg_reading: process(clk_i)
p_reg_reading: process(clk_i)
begin
if rising_edge(clk_i) then
if core_rst = '1' then
......@@ -998,16 +998,16 @@ begin
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL <= CONTROL;
-- CLK <= clk_i;
-- TRIG0 <= TRIG0;
-- TRIG1 <= TRIG1;
-- TRIG2 <= TRIG2;
-- TRIG3 <= TRIG3);
-- port map
-- (CONTROL => CONTROL;
-- CLK => clk_i;
-- TRIG0 => TRIG0;
-- TRIG1 => TRIG1;
-- TRIG2 => TRIG2;
-- TRIG3 => TRIG3);
-- chipscope_icon_1 : chipscope_icon
-- port map ( CONTROL0 <= CONTROL);
-- port map ( CONTROL0 => CONTROL);
-- TRIG0(8 downto 0) <= reg_from_mt.tx_ctrl_bytes_num_o;
-- TRIG0(18 downto 11) <= tx_ctrl_byte;
......@@ -1030,6 +1030,9 @@ begin
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
\ No newline at end of file
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
......@@ -235,7 +235,7 @@ begin
cmp_rx_osc: wf_rx_osc
port map(
uclk_i => clk_i,
rate_i => speed_i, -- or rx_rst??
rate_i => speed_i,
nfip_rst_i => rst_i,
fd_rxd_edge_p_i => rxd_filt_edge_p,
rx_osc_rst_i => rx_osc_rst,
......@@ -260,14 +260,14 @@ begin
-------------------------------------------------------
counter_o => rx_byte_index);
-------------------------------------------------------
bytes_c_rst <= '1' when (rst_i = '1' or rx_rst_i = '1') else '0';
bytes_c_rst <= rst_i or rx_rst_i;
rx_byte_index_o <= rx_byte_index;
---------------------------------------------------------------------------------------------------
-- combination of four retrieved bytes to a 32-bit word --
---------------------------------------------------------------------------------------------------
create_32bit_words: process (clk_i)
p_create_32bit_words: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
......@@ -297,7 +297,7 @@ begin
---------------------------------------------------------------------------------------------------
-- transfer 32bit words to the cons_frame registers
delay: process (clk_i)
p_delay: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
......@@ -311,7 +311,7 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
data_transfer_to_regs: process (clk_i)
p_data_transfer_to_regs: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
......@@ -349,7 +349,7 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rx_word_index_o <= std_logic_vector(to_unsigned(word32_num,C_FRAME_WORDS_CNT_LGTH));
......
......@@ -189,7 +189,7 @@ begin
-- All the frame bytes are copied to local registers; like this the frame data remain stable
-- until the next tx_start_p_i arrives.
data_retrieval: process (clk_i)
p_data_retrieval: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
......@@ -219,7 +219,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Selection of one 32-bit word of the prod_frame words array
select_word: process (clk_i)
p_select_word: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
......
......@@ -3,8 +3,8 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_csr.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 06/30/17 10:03:28
-- Version : 0x00000001
-- Created : 06/30/17 14:35:27
-- Version : 0x00010000
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -157,7 +157,7 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
masterfip_ver_id_int <= "00000000000000000000000000000001";
masterfip_ver_id_int <= "00000000000000010000000000000000";
masterfip_rst_core_int <= '0';
masterfip_rst_fd_int <= '0';
masterfip_led_rx_act_int <= '0';
......
......@@ -3,8 +3,8 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 06/30/17 10:03:28
-- Version : 0x00000001
-- Created : 06/30/17 14:35:27
-- Version : 0x00010000
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......
......@@ -3,8 +3,8 @@
* File : masterfip_wbgen2_csr.h
* Author : auto-generated by wbgen2 from masterfip_csr.wb
* Created : 06/30/17 10:03:28
* Version : 0x00000001
* Created : 06/30/17 14:35:28
* Version : 0x00010000
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -36,7 +36,7 @@
#endif
/* version definition */
#define WBGEN2_MASTERFIP_VERSION 0x00000001
#define WBGEN2_MASTERFIP_VERSION 0x00010000
/* definitions for register: Version register */
......
......@@ -29,7 +29,7 @@
<BODY>
<h1 class="heading">masterfip_wbgen2_csr</h1>
<h3>FMC masterFIP core registers</h3>
<h3>[version 0x00000001]</h3>
<h3>[version 0x00010000]</h3>
<p>Wishbone slave for FMC masterFIP core</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
......
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......@@ -267,8 +267,11 @@ NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "l_rst_n_i" TIG;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
\ No newline at end of file
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/06/30
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_cmp_mock_turtle_gen_with_gennum_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" 20 ns HIGH 50%;
......@@ -523,7 +523,7 @@ begin
---------------------------------------------------------------------------------------------------
-- SPEC front panel LEDs --
---------------------------------------------------------------------------------------------------
drive_led_clk_sys: process (clk_100m_sys)
p_drive_spec_led_clk_sys: process (clk_100m_sys)
begin
if rising_edge(clk_100m_sys) then
if(rst_n_sys = '0') then
......
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