- 29 Jul, 2021 2 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
Add VHDL Library support to ISE See merge request !7
-
- 28 Jul, 2021 3 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 26 Jul, 2021 2 commits
-
-
Phil Clarke authored
-
Phil Clarke authored
-
- 01 Jul, 2021 1 commit
-
-
Tristan Gingold authored
-
- 30 Jun, 2021 5 commits
-
-
Tristan Gingold authored
Simplify the code. Adjust baselines
-
Tristan Gingold authored
-
Tristan Gingold authored
Fix #112 the default library on Xilinx is xil_default, which is also the library where XCI designs are put. If the default library is 'work', then an instantiation like 'entity work.ip' will look in library 'work' which doesn't contain XCI designs. Adjust baselines
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 21 Jun, 2021 7 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 17 Jun, 2021 5 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
Adjust baseline
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 16 Jun, 2021 1 commit
-
-
Tristan Gingold authored
-
- 10 Jun, 2021 1 commit
-
-
Tristan Gingold authored
extract the provided unit
-
- 25 May, 2021 5 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
clarify code. Fix #111
-
- 21 May, 2021 8 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-