[Vivado] Source files generated from IP customization files (xci) not included in library 'work'
After 4e09765b synthesis fails for projects that make use of IP generated from xci files. Changing _XILINX_VHDL_PROPERTY
to None
fixes this issue (at least for vhdl projects).
https://ohwr.org/project/hdl-make/blob/develop/hdlmake/tools/xilinx_prj.py#L38-39
Minimal reproducible example attached, execute:
$ hdlmake
$ make synthesize
Vivado version: 2018.3
Platform: Ubuntu Linux 20.04 x86-64