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Commit 7a78578e authored by Tristan Gingold's avatar Tristan Gingold
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testsuite: add a test for #112

parent 5938daae
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Showing with 240 additions and 9 deletions
testsuite/104xci/Makefile.ref 0 → 100644
View file @ 7a78578e
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := xci_test
PROJECT := xci_test
PROJECT_FILE := $(PROJECT).xpr
TOOL_PATH :=
TCL_INTERPRETER := vivado -mode tcl -source
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY :=
SYN_DEVICE := xc7a200t
SYN_PACKAGE := ffg1156
SYN_GRADE := -2
TCL_CREATE := create_project $(PROJECT) ./
TCL_OPEN := open_project $(PROJECT_FILE)
TCL_CLOSE := exit
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
files.tcl:
@echo add_files -norecurse "{" >> $@
@echo "vio_din2_w64_dout2_w64.xci" >> $@
@echo "xci_test.vhd" >> $@
@echo "}" >> $@
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo # project properties >> $@
echo set_property "part" "$(SYN_DEVICE)$(SYN_PACKAGE)$(SYN_GRADE)" [current_project] >> $@
echo set_property "target_language" "vhdl" [current_project] >> $@
echo set_property "top" "$(TOP_MODULE)" [get_property srcset [current_run]] >> $@
echo source files.tcl >> $@
echo update_compile_order -fileset sources_1 >> $@
echo update_compile_order -fileset sim_1 >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo # synthesize properties >> $@
echo reset_run synth_1 >> $@
echo launch_runs synth_1 >> $@
echo wait_on_run synth_1 >> $@
echo set result [get_property STATUS [get_runs synth_1]] >> $@
echo set keyword [lindex [split '$$'result " "] end] >> $@
echo if { '$$'keyword != \"Complete!\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_CLOSE) >> $@
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo # par properties >> $@
echo reset_run impl_1 >> $@
echo launch_runs impl_1 >> $@
echo wait_on_run impl_1 >> $@
echo set result [get_property STATUS [get_runs impl_1]] >> $@
echo set keyword [lindex [split '$$'result " "] end] >> $@
echo if { '$$'keyword != \"Complete!\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_CLOSE) >> $@
par: synthesize par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo launch_runs impl_1 -to_step write_bitstream >> $@
echo wait_on_run impl_1 >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) .Xil *.jou *.log *.pb *.dmp $(PROJECT).cache $(PROJECT).data work $(PROJECT).runs $(PROJECT).hw $(PROJECT).sim $(PROJECT).ip_user_files $(PROJECT_FILE)
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin
.PHONY: mrproper clean all
testsuite/104xci/Manifest.py 0 → 100644
View file @ 7a78578e
target = "xilinx"
action = "synthesis"
syn_device = "xc7a200t"
syn_grade = "-2"
syn_package = "ffg1156"
syn_top = "xci_test"
syn_project = "xci_test"
syn_tool = "vivado"
files = [
"vio_din2_w64_dout2_w64.xci",
"xci_test.vhd",
]
testsuite/104xci/vio_din2_w64_dout2_w64.xci 0 → 100644
View file @ 7a78578e
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>vio_din2_w64_dout2_w64</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="vio" spirit:version="3.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PROBE_IN">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PROBE_OUT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">artix7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_SYNCHRONIZATION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_IN">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN0_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN1_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT0_INIT_VAL">0x0000000000000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT0_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT1_INIT_VAL">0x0000000000000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT1_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">vio_din2_w64_dout2_w64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg1156</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">19</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2018.3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_PROBE_IN" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE_IN0_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE_IN1_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE_OUT0_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE_OUT1_WIDTH" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
testsuite/104xci/xci_test.vhd 0 → 100644
View file @ 7a78578e
library ieee;
use ieee.std_logic_1164.all;
entity xci_test is
port(
clk_i: in std_logic;
data_o: out std_logic_vector(63 downto 0)
);
end xci_test;
architecture xci_test_arch of xci_test is
begin
cmp_vio_din2_w64_dout2_w64 : entity work.vio_din2_w64_dout2_w64
port map (
clk => clk_i,
probe_in0 => (others => '0'),
probe_in1 => (others => '0'),
probe_out0 => data_o,
probe_out1 => open
);
end xci_test_arch;
testsuite/test_all.py
View file @ 7a78578e
......@@ -120,30 +120,30 @@ def test_icestorm():
hdlmake.main.hdlmake([])
compare_makefile_filter("TOOL_PATH")
def test_isim_010():
def test_isim010():
with Config(path="010isim") as _:
hdlmake.main.hdlmake([])
compare_makefile_xilinx()
def test_isim_windows_060():
def test_isim_windows060():
with Config(path="060isim_windows",
my_os='windows', fakebin="windows_fakebin") as _:
hdlmake.main.hdlmake([])
compare_makefile_xilinx()
def test_icarus_012():
def test_icarus012():
run_compare(path="012icarus")
def test_icarus_include_083():
run_compare(path="083icarus_include")
def test_libero():
def test_libero013():
run_compare(path="013libero")
def test_planahead():
def test_planahead014():
run_compare(path="014planahead")
def test_quartus():
def test_quartus015():
run_compare(path="015quartus")
def test_quartus016():
......@@ -185,10 +185,10 @@ def test_quartus039():
run([], path="039quartus_err")
#os.remove('039quartus_err/Makefile')
def test_riviera():
def test_riviera017():
run_compare(path="017riviera")
def test_vivado():
def test_vivado018():
run_compare(path="018vivado")
def test_vivado_props():
......@@ -269,9 +269,12 @@ def test_err_fetch():
run([], path="065fetch_pre_post")
assert False
def test_xci():
def test_xci023():
run_compare(path="023xci")
def test_xci104():
run_compare(path="104xci")
def test_vlog_parser024():
run_compare(path="024vlog_parser")
......
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