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Hdlmake
Commit e9b5dc57 authored by Tristan Gingold's avatar Tristan Gingold
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make_sim: rename class from ToolSim to MakeSim.

parent e771d984
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Showing with 14 additions and 14 deletions
hdlmake/tools/active_hdl.py
View file @ e9b5dc57
...@@ -24,11 +24,11 @@ ...@@ -24,11 +24,11 @@
"""Module providing support for Aldec Active-HDL simulator""" """Module providing support for Aldec Active-HDL simulator"""
from __future__ import absolute_import from __future__ import absolute_import
from .make_sim import ToolSim from .make_sim import MakeSim
from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile
class ToolActiveHDL(ToolSim): class ToolActiveHDL(MakeSim):
"""Class providing the interface to control an Active-HDL simulation""" """Class providing the interface to control an Active-HDL simulation"""
......
hdlmake/tools/ghdl.py
View file @ e9b5dc57
...@@ -26,11 +26,11 @@ ...@@ -26,11 +26,11 @@
from __future__ import absolute_import from __future__ import absolute_import
import string import string
from .make_sim import ToolSim from .make_sim import MakeSim
from hdlmake.srcfile import VHDLFile from hdlmake.srcfile import VHDLFile
class ToolGHDL(ToolSim): class ToolGHDL(MakeSim):
"""Class providing the interface for GHDL simulator""" """Class providing the interface for GHDL simulator"""
......
hdlmake/tools/isim.py
View file @ e9b5dc57
...@@ -30,12 +30,12 @@ import os ...@@ -30,12 +30,12 @@ import os
import os.path import os.path
import logging import logging
from .make_sim import ToolSim from .make_sim import MakeSim
from hdlmake.util import shell from hdlmake.util import shell
from hdlmake.srcfile import VerilogFile, VHDLFile from hdlmake.srcfile import VerilogFile, VHDLFile
class ToolISim(ToolSim): class ToolISim(MakeSim):
"""Class providing the interface for Xilinx ISim simulator""" """Class providing the interface for Xilinx ISim simulator"""
......
hdlmake/tools/iverilog.py
View file @ e9b5dc57
...@@ -26,11 +26,11 @@ ...@@ -26,11 +26,11 @@
from __future__ import absolute_import from __future__ import absolute_import
import string import string
from .make_sim import ToolSim from .make_sim import MakeSim
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
class ToolIVerilog(ToolSim): class ToolIVerilog(MakeSim):
"""Class providing the interface for Icarus Verilog simulator""" """Class providing the interface for Icarus Verilog simulator"""
......
hdlmake/tools/make_sim.py
View file @ e9b5dc57
...@@ -16,12 +16,12 @@ def _check_simulation_manifest(manifest_dict): ...@@ -16,12 +16,12 @@ def _check_simulation_manifest(manifest_dict):
raise Exception("sim_top variable must be set in the top manifest.") raise Exception("sim_top variable must be set in the top manifest.")
class ToolSim(ToolMakefile): class MakeSim(ToolMakefile):
"""Class that provides the Makefile writing methods and status""" """Class that provides the Makefile writing methods and status"""
def __init__(self): def __init__(self):
super(ToolSim, self).__init__() super(MakeSim, self).__init__()
self._simulator_controls = {} self._simulator_controls = {}
def write_makefile(self, config, fileset, filename=None): def write_makefile(self, config, fileset, filename=None):
......
hdlmake/tools/sim_makefile_support.py
View file @ e9b5dc57
...@@ -27,13 +27,13 @@ from __future__ import absolute_import ...@@ -27,13 +27,13 @@ from __future__ import absolute_import
import os import os
import string import string
from .make_sim import ToolSim from .make_sim import MakeSim
from hdlmake.util import shell from hdlmake.util import shell
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
import six import six
class VsimMakefileWriter(ToolSim): class VsimMakefileWriter(MakeSim):
"""A Makefile writer for simulation suitable for vsim based simulators. """A Makefile writer for simulation suitable for vsim based simulators.
......
hdlmake/tools/vivado_sim.py
View file @ e9b5dc57
...@@ -25,10 +25,10 @@ ...@@ -25,10 +25,10 @@
from __future__ import absolute_import from __future__ import absolute_import
from .make_sim import ToolSim from .make_sim import MakeSim
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
class ToolVivadoSim(ToolSim): class ToolVivadoSim(MakeSim):
"""Class providing the interface for Xilinx Vivado synthesis""" """Class providing the interface for Xilinx Vivado synthesis"""
......
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