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Hdlmake
Commit e771d984 authored by Tristan Gingold's avatar Tristan Gingold
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Rename ToolSyn to MakeSyn (to match the file name).

parent d9c5d66a
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Showing with 15 additions and 15 deletions
hdlmake/tools/diamond.py
View file @ e771d984
......@@ -25,11 +25,11 @@
from __future__ import absolute_import
from .make_syn import ToolSyn
from .make_syn import MakeSyn
from hdlmake.srcfile import EDFFile, LPFFile, VHDLFile, VerilogFile
class ToolDiamond(ToolSyn):
class ToolDiamond(MakeSyn):
"""Class providing the interface for Lattice Diamond synthesis"""
......
hdlmake/tools/icestorm.py
View file @ e771d984
......@@ -25,11 +25,11 @@
from __future__ import absolute_import
from .make_syn import ToolSyn
from .make_syn import MakeSyn
from hdlmake.srcfile import VerilogFile, PCFFile
class ToolIcestorm(ToolSyn):
class ToolIcestorm(MakeSyn):
"""Class providing the interface for IceStorm synthesis"""
......
hdlmake/tools/ise.py
View file @ e771d984
......@@ -27,7 +27,7 @@ from __future__ import print_function
from __future__ import absolute_import
import logging
from .make_syn import ToolSyn
from .make_syn import MakeSyn
from hdlmake.util import shell
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
......@@ -48,7 +48,7 @@ ISE_STANDARD_LIBS = ['ieee', 'ieee_proposed', 'iSE', 'simprims', 'std',
'synopsys', 'unimacro', 'unisim', 'XilinxCoreLib']
class ToolISE(ToolSyn):
class ToolISE(MakeSyn):
"""Class providing the methods to create and build a Xilinx ISE project"""
......@@ -108,7 +108,7 @@ $(TCL_CLOSE)'''
'save': 'project save',
'close': 'project close',
'project': '$(TCL_CREATE)\n'
'xfile remove [search \* -type file]\n'
'xfile remove [search \\* -type file]\n'
'source files.tcl\n'
'{0}\n'
'project set top $(TOP_MODULE)\n'
......
hdlmake/tools/libero.py
View file @ e771d984
......@@ -25,11 +25,11 @@
from __future__ import absolute_import
from .make_syn import ToolSyn
from .make_syn import MakeSyn
from hdlmake.srcfile import VHDLFile, VerilogFile, SDCFile, PDCFile
class ToolLibero(ToolSyn):
class ToolLibero(MakeSyn):
"""Class providing the interface for Microsemi Libero IDE synthesis"""
......
hdlmake/tools/make_syn.py
View file @ e771d984
......@@ -21,12 +21,12 @@ def _check_synthesis_manifest(manifest_dict):
"syn_top variable must be set in the top manifest.")
class ToolSyn(ToolMakefile):
class MakeSyn(ToolMakefile):
"""Class that provides the synthesis Makefile writing methods and status"""
def __init__(self):
super(ToolSyn, self).__init__()
super(MakeSyn, self).__init__()
def write_makefile(self, config, fileset, filename=None):
"""Generate a Makefile for the specific synthesis tool"""
......
hdlmake/tools/quartus.py
View file @ e771d984
......@@ -28,7 +28,7 @@ import os
import sys
import logging
from .make_syn import ToolSyn
from .make_syn import MakeSyn
from hdlmake.util import path as path_mod
from hdlmake.util import shell
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, DPFFile,
......@@ -36,7 +36,7 @@ from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, DPFFile,
QSFFile, BSFFile, BDFFile, TDFFile, GDFFile)
class ToolQuartus(ToolSyn):
class ToolQuartus(MakeSyn):
"""Class providing the interface for Altera Quartus synthesis"""
......
hdlmake/tools/xilinx.py
View file @ e771d984
......@@ -25,12 +25,12 @@
from __future__ import absolute_import
from .make_syn import ToolSyn
from .make_syn import MakeSyn
from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile, TCLFile
import logging
class ToolXilinx(ToolSyn):
class ToolXilinx(MakeSyn):
"""Class providing the interface for Xilinx Vivado synthesis"""
......
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