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Hdlmake
Commits
e9b5dc57
Commit
e9b5dc57
authored
Sep 19, 2019
by
Tristan Gingold
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make_sim: rename class from ToolSim to MakeSim.
parent
e771d984
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7 changed files
with
14 additions
and
14 deletions
+14
-14
active_hdl.py
hdlmake/tools/active_hdl.py
+2
-2
ghdl.py
hdlmake/tools/ghdl.py
+2
-2
isim.py
hdlmake/tools/isim.py
+2
-2
iverilog.py
hdlmake/tools/iverilog.py
+2
-2
make_sim.py
hdlmake/tools/make_sim.py
+2
-2
sim_makefile_support.py
hdlmake/tools/sim_makefile_support.py
+2
-2
vivado_sim.py
hdlmake/tools/vivado_sim.py
+2
-2
No files found.
hdlmake/tools/active_hdl.py
View file @
e9b5dc57
...
...
@@ -24,11 +24,11 @@
"""Module providing support for Aldec Active-HDL simulator"""
from
__future__
import
absolute_import
from
.make_sim
import
Tool
Sim
from
.make_sim
import
Make
Sim
from
hdlmake.srcfile
import
VHDLFile
,
VerilogFile
,
SVFile
class
ToolActiveHDL
(
Tool
Sim
):
class
ToolActiveHDL
(
Make
Sim
):
"""Class providing the interface to control an Active-HDL simulation"""
...
...
hdlmake/tools/ghdl.py
View file @
e9b5dc57
...
...
@@ -26,11 +26,11 @@
from
__future__
import
absolute_import
import
string
from
.make_sim
import
Tool
Sim
from
.make_sim
import
Make
Sim
from
hdlmake.srcfile
import
VHDLFile
class
ToolGHDL
(
Tool
Sim
):
class
ToolGHDL
(
Make
Sim
):
"""Class providing the interface for GHDL simulator"""
...
...
hdlmake/tools/isim.py
View file @
e9b5dc57
...
...
@@ -30,12 +30,12 @@ import os
import
os.path
import
logging
from
.make_sim
import
Tool
Sim
from
.make_sim
import
Make
Sim
from
hdlmake.util
import
shell
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
class
ToolISim
(
Tool
Sim
):
class
ToolISim
(
Make
Sim
):
"""Class providing the interface for Xilinx ISim simulator"""
...
...
hdlmake/tools/iverilog.py
View file @
e9b5dc57
...
...
@@ -26,11 +26,11 @@
from
__future__
import
absolute_import
import
string
from
.make_sim
import
Tool
Sim
from
.make_sim
import
Make
Sim
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
class
ToolIVerilog
(
Tool
Sim
):
class
ToolIVerilog
(
Make
Sim
):
"""Class providing the interface for Icarus Verilog simulator"""
...
...
hdlmake/tools/make_sim.py
View file @
e9b5dc57
...
...
@@ -16,12 +16,12 @@ def _check_simulation_manifest(manifest_dict):
raise
Exception
(
"sim_top variable must be set in the top manifest."
)
class
Tool
Sim
(
ToolMakefile
):
class
Make
Sim
(
ToolMakefile
):
"""Class that provides the Makefile writing methods and status"""
def
__init__
(
self
):
super
(
Tool
Sim
,
self
)
.
__init__
()
super
(
Make
Sim
,
self
)
.
__init__
()
self
.
_simulator_controls
=
{}
def
write_makefile
(
self
,
config
,
fileset
,
filename
=
None
):
...
...
hdlmake/tools/sim_makefile_support.py
View file @
e9b5dc57
...
...
@@ -27,13 +27,13 @@ from __future__ import absolute_import
import
os
import
string
from
.make_sim
import
Tool
Sim
from
.make_sim
import
Make
Sim
from
hdlmake.util
import
shell
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
import
six
class
VsimMakefileWriter
(
Tool
Sim
):
class
VsimMakefileWriter
(
Make
Sim
):
"""A Makefile writer for simulation suitable for vsim based simulators.
...
...
hdlmake/tools/vivado_sim.py
View file @
e9b5dc57
...
...
@@ -25,10 +25,10 @@
from
__future__
import
absolute_import
from
.make_sim
import
Tool
Sim
from
.make_sim
import
Make
Sim
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
class
ToolVivadoSim
(
Tool
Sim
):
class
ToolVivadoSim
(
Make
Sim
):
"""Class providing the interface for Xilinx Vivado synthesis"""
...
...
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