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Hdlmake
Commit 1fb93c1b authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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IVerilog tool relies on Make to create an ordered file list

parent 378ef626
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Showing with 34 additions and 21 deletions
hdlmake/tools/iverilog.py
View file @ 1fb93c1b
...@@ -23,9 +23,11 @@ ...@@ -23,9 +23,11 @@
"""Module providing support for IVerilog (Icarus Verilog) simulator""" """Module providing support for IVerilog (Icarus Verilog) simulator"""
import os
import string import string
from .make_sim import ToolSim from .make_sim import ToolSim
from hdlmake.util import path as path_mod
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
...@@ -43,7 +45,7 @@ class ToolIVerilog(ToolSim): ...@@ -43,7 +45,7 @@ class ToolIVerilog(ToolSim):
HDL_FILES = [VerilogFile, VHDLFile, SVFile] HDL_FILES = [VerilogFile, VHDLFile, SVFile]
CLEAN_TARGETS = {'clean': ["run.command", "ivl_vhdl_work"], CLEAN_TARGETS = {'clean': ["run.command", "ivl_vhdl_work", "work"],
'mrproper': ["*.vcd", "*.vvp"]} 'mrproper': ["*.vcd", "*.vvp"]}
def __init__(self): def __init__(self):
...@@ -56,30 +58,41 @@ class ToolIVerilog(ToolSim): ...@@ -56,30 +58,41 @@ class ToolIVerilog(ToolSim):
"""Generate compile simulation Makefile target for IVerilog""" """Generate compile simulation Makefile target for IVerilog"""
fileset = self.fileset fileset = self.fileset
top_module = self.top_module top_module = self.top_module
self.writeln("simulation: include_dirs $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("simulation:") self.writeln("\t\tiverilog $(IVERILOG_OPT) -s $(TOP_MODULE)"
" -o $(TOP_MODULE).vvp -c run.command")
self.writeln()
self.writeln("include_dirs:")
self.writeln("\t\techo \"# IVerilog command file," self.writeln("\t\techo \"# IVerilog command file,"
" generated by HDLMake\" > run.command") " generated by HDLMake\" > run.command")
self.writeln()
for inc in top_module.get_include_dirs_list(): for inc in top_module.get_include_dirs_list():
self.writeln("\t\techo \"+incdir+" + inc + "\" >> run.command") self.writeln("\t\techo \"+incdir+" + inc + "\" >> run.command")
self.writeln('\n')
for vlog in fileset.filter(VerilogFile): for file_aux in fileset:
self.writeln("\t\techo \"" + vlog.rel_path() + "\" >> run.command") if any(isinstance(file_aux, file_type)
for file_type in [VerilogFile, SVFile, VHDLFile]):
for vhdl in fileset.filter(VHDLFile): self.write("%s: %s" % (os.path.join(
self.writeln("\t\techo \"" + vhdl.rel_path() + "\" >> run.command") file_aux.library, file_aux.purename,
".%s_%s" % (file_aux.purename, file_aux.extension())),
for svlog in fileset.filter(SVFile): file_aux.rel_path()))
self.writeln( # list dependencies, do not include the target file
"\t\techo \"" + for dep_file in [dfile for dfile in file_aux.depends_on
svlog.rel_path( if dfile is not file_aux]:
) + if dep_file in fileset:
"\" >> run.command") name = dep_file.purename
extension = dep_file.extension()
self.writeln("\t\tiverilog $(IVERILOG_OPT) -s $(TOP_MODULE)" self.write(" \\\n" + os.path.join(
" -o $(TOP_MODULE).vvp -c run.command") dep_file.library, name, ".%s_%s" %
(name, extension)))
else:
# the file is included -> we depend directly on it
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
self.writeln("\t\techo $< >> run.command")
self.write("\t\t@" + path_mod.mkdir_command() + " $(dir $@)")
self.writeln(" && touch $@ \n")
self.writeln()
def makefile_sim_options(self): def makefile_sim_options(self):
"""Print the IVerilog options to the Makefile""" """Print the IVerilog options to the Makefile"""
......
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