Several code style fixes applied to different files

parent 1538e3ae
......@@ -160,19 +160,19 @@ def _get_parser():
usage=usage,
description=description)
subparsers = parser.add_subparsers(title="commands", dest="command")
manifest_help = subparsers.add_parser(
subparsers.add_parser(
"manifest-help",
help="print manifest file variables description")
make_simulation = subparsers.add_parser(
subparsers.add_parser(
"make-simulation",
help="generate simulation makefile")
make_synthesis = subparsers.add_parser(
subparsers.add_parser(
"make-synthesis",
help="generate synthesis makefile")
fetch = subparsers.add_parser(
subparsers.add_parser(
"fetch",
help="fetch and/or update remote modules listed in Manifest")
clean = subparsers.add_parser(
subparsers.add_parser(
"clean",
help="remove all modules fetched for direct and indirect "
"children of this module")
......
......@@ -66,17 +66,8 @@ class ActionSimulation(Action):
sys.exit("Exiting")
tool_object = tool_dict[tool_name]
tool_info = tool_object.TOOL_INFO
if sys.platform == 'cygwin':
bin_name = tool_info['windows_bin']
else:
bin_name = tool_info['linux_bin']
path_key = tool_info['id'] + '_path'
name = tool_info['name']
self.env.check_tool(tool_object)
if self.env[path_key] is None and self.env.options.force is not True:
logging.error("Can't generate a " + name + " makefile. " +
bin_name + " not found.")
sys.exit("Exiting")
logging.info("Generating " + name + " makefile for simulation.")
top_module = self.get_top_module()
fset = self.build_file_set(top_module.manifest_dict["sim_top"],
......
......@@ -38,7 +38,7 @@ class DepParser(object):
def parse(self, dep_file):
"""Base dummy interface method for the HDL parse execution"""
raise
pass
def solve(fileset, standard_libs=None):
"""Function that Parses and Solves the provided HDL fileset. Note
......
......@@ -39,11 +39,7 @@ class ToolIVerilog(ToolSim):
'windows_bin': 'iverilog',
'linux_bin': 'iverilog'}
STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
'simprim', 'unisim', 'unimacro', 'aim', 'cpld',
'pls', 'xilinxcorelib', 'aim_ver', 'cpld_ver',
'simprims_ver', 'unisims_ver', 'uni9000_ver',
'unimacro_ver', 'xilinxcorelib_ver', 'secureip']
STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys']
HDL_FILES = [VerilogFile, VHDLFile, SVFile]
......
"""This package provides common utils... but not used ad package yet!"""
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment