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Hdlmake
Commits
1fb93c1b
Commit
1fb93c1b
authored
Aug 09, 2016
by
Javier D. Garcia-Lasheras
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IVerilog tool relies on Make to create an ordered file list
parent
378ef626
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1 changed file
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34 additions
and
21 deletions
+34
-21
iverilog.py
hdlmake/tools/iverilog.py
+34
-21
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hdlmake/tools/iverilog.py
View file @
1fb93c1b
...
...
@@ -23,9 +23,11 @@
"""Module providing support for IVerilog (Icarus Verilog) simulator"""
import
os
import
string
from
.make_sim
import
ToolSim
from
hdlmake.util
import
path
as
path_mod
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
...
...
@@ -43,7 +45,7 @@ class ToolIVerilog(ToolSim):
HDL_FILES
=
[
VerilogFile
,
VHDLFile
,
SVFile
]
CLEAN_TARGETS
=
{
'clean'
:
[
"run.command"
,
"ivl_vhdl_work"
],
CLEAN_TARGETS
=
{
'clean'
:
[
"run.command"
,
"ivl_vhdl_work"
,
"work"
],
'mrproper'
:
[
"*.vcd"
,
"*.vvp"
]}
def
__init__
(
self
):
...
...
@@ -56,30 +58,41 @@ class ToolIVerilog(ToolSim):
"""Generate compile simulation Makefile target for IVerilog"""
fileset
=
self
.
fileset
top_module
=
self
.
top_module
self
.
writeln
(
"simulation:"
)
self
.
writeln
(
"simulation: include_dirs $(VERILOG_OBJ) $(VHDL_OBJ)"
)
self
.
writeln
(
"
\t\t
iverilog $(IVERILOG_OPT) -s $(TOP_MODULE)"
" -o $(TOP_MODULE).vvp -c run.command"
)
self
.
writeln
()
self
.
writeln
(
"include_dirs:"
)
self
.
writeln
(
"
\t\t
echo
\"
# IVerilog command file,"
" generated by HDLMake
\"
> run.command"
)
self
.
writeln
()
for
inc
in
top_module
.
get_include_dirs_list
():
self
.
writeln
(
"
\t\t
echo
\"
+incdir+"
+
inc
+
"
\"
>> run.command"
)
for
vlog
in
fileset
.
filter
(
VerilogFile
):
self
.
writeln
(
"
\t\t
echo
\"
"
+
vlog
.
rel_path
()
+
"
\"
>> run.command"
)
for
vhdl
in
fileset
.
filter
(
VHDLFile
):
self
.
writeln
(
"
\t\t
echo
\"
"
+
vhdl
.
rel_path
()
+
"
\"
>> run.command"
)
for
svlog
in
fileset
.
filter
(
SVFile
):
self
.
writeln
(
"
\t\t
echo
\"
"
+
svlog
.
rel_path
(
)
+
"
\"
>> run.command"
)
self
.
writeln
(
"
\t\t
iverilog $(IVERILOG_OPT) -s $(TOP_MODULE)"
" -o $(TOP_MODULE).vvp -c run.command"
)
self
.
writeln
(
'
\n
'
)
for
file_aux
in
fileset
:
if
any
(
isinstance
(
file_aux
,
file_type
)
for
file_type
in
[
VerilogFile
,
SVFile
,
VHDLFile
]):
self
.
write
(
"
%
s:
%
s"
%
(
os
.
path
.
join
(
file_aux
.
library
,
file_aux
.
purename
,
".
%
s_
%
s"
%
(
file_aux
.
purename
,
file_aux
.
extension
())),
file_aux
.
rel_path
()))
# list dependencies, do not include the target file
for
dep_file
in
[
dfile
for
dfile
in
file_aux
.
depends_on
if
dfile
is
not
file_aux
]:
if
dep_file
in
fileset
:
name
=
dep_file
.
purename
extension
=
dep_file
.
extension
()
self
.
write
(
"
\\\n
"
+
os
.
path
.
join
(
dep_file
.
library
,
name
,
".
%
s_
%
s"
%
(
name
,
extension
)))
else
:
# the file is included -> we depend directly on it
self
.
write
(
"
\\\n
"
+
dep_file
.
rel_path
())
self
.
writeln
()
self
.
writeln
(
"
\t\t
echo $< >> run.command"
)
self
.
write
(
"
\t\t
@"
+
path_mod
.
mkdir_command
()
+
" $(dir $@)"
)
self
.
writeln
(
" && touch $@
\n
"
)
self
.
writeln
()
def
makefile_sim_options
(
self
):
"""Print the IVerilog options to the Makefile"""
...
...
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