Purpose
The GSI Timing Starter Kit is a functional snapshot of the eventual FAIR timing system, which is under active development. It demonstrates real-time coordination of two front-end equipment controllers. The product consists of a data master (Linux PC) which coordinates events, a timing master which synchronizes clocks (White Rabbit switch), and two front-end equipment controllers (either SPECv4 or SCUv2).
Features
Functionality demonstrated:
- Clock synchronization of front-end controllers (FEC) using White Rabbit
- Coordinated, preprogrammed, synchronous event generation by multiple FECs
- Capturing the timestamp of an incoming signal on a FEC
- Reading the current time from host systems.
FECs can be controlled via:
- Etherbone over the timing network
- PCI express to the host system (using Etherbone)
- The Etherbone C/C** library API
- Command-line Etherbone tools
- Command-line timing scripts
Requirements
To use the GSI Timing Starter Kit you will need:
- 1x Linux PC to serve as Data Master (DM)
- 1x White Rabbit v3 switch
- 2x Supported FECs (either SCUv2 or SPECv4)
- SFPs and cables to connect FECs and DM to switch
- (Optional) JTAG cables suitable for flashing chosen FECs
- (Optional) Linux host system for SPECv4 cards
- (Optional) USB boot stick for SCU (x86 linux)
Setup
If the FECs were not preloaded with the starter kit, you will need to program them. You can use these Prebuilt-images for the SCUv2 and SPECv4 or follow the directions for Building-from-sources. Once you have the
program flash
configure a data master = BOOTP server
(optional) configure host system--linux or SCU
Interfaces
White-Rabbit Console
PCIe bridge access from host
Etherbone access from data master
Timing shell scripts
Register maps
Bus layout
ECA
TLU