Flash an Altera device (SPI Flash Memory)
The flashing procedure should proceed smoothly according the Altera doc:
Using the Serial FlashLoader with the Quartus II Software
Unfortunately we have four design based on Altera FPGAs, and two out of four, need a workaround. A standard flashing is described in the section of the EXPLODER, using a bash script in the SCU section, and finally the section of VETAR, describes a still not well explained by Altera recipe.
Flashing the EXPLODER
Connect the JTAG to your EXPLODER and follow the document Using the Serial FlashLoader with the Quartus II Software .
Flashing the SCU
Connect JTAG to your SCU as shown in the diagram:
SCUv2-jtag.jpeg
You must also power the SCU by either installing it in a rack or
connecting external power as illustrated.
Given a working jam file (you can use Prebuilt-images), you reprogram the flash of an SCU by executing these commands:
quartus_jli -aerase <jam-file>
quartus_jli -aerase -ddo_epcs_bulk_erase=1 <jam-file>
quartus_jli -ablankcheck <jam-file>
quartus_jli -aprogram <jam-file>
quartus_jli -averify <jam-file>
If you have the sources available (see Building-from-sources), you can simply run:
./scripts/program-scu.sh wr-cores/syn/gsi_scu2/wr_core_demo/scu2.jam
Now that your device is flashed, confirm that it working using the White-Rabbit-Console.
Flashing the VETAR
The flashing of the SPI of a VETAR card is not a standard procedure. Please follow the recipe:
SFL Megafunction
Altera provides a Serial Flash Loader Megafunction that enables the flashing of a SPI Flash, once the FPGA is programed with a bitstream containing this Megafunction. Please, use the "Enhanced" option, if not, you will be not able to program the flash:
Code snippet:
component flash_loader_asmi
port (
asdo_in : in std_logic;
asmi_access_granted : in std_logic;
dclk_in : in std_logic;
ncso_in : in std_logic;
noe_in : in std_logic;
asmi_access_request : out std_logic;
data0_out : out std_logic);
end component; serial_flash_loader : flash_loader_asmi
..
..
...
....
......
port map(
asdo_in => sink,
asmi_access_granted => '1',
dclk_in => clk_20m_vcxo_i, -- Clock signal from user design to DCLK.
ncso_in => '0',
noe_in => '0',
asmi_access_request => open,
data0_out => open);
Example project of the Enhanced Serial Flash Loader
File Conversion
You need now to convert the jam file to .jic, "JTAG Inderect Configuration", go to File-> Convert Programming Files:
- Select Programming file type: .jic
- Configure device: EPCS128 mode: Active serial
- Input files to convert:
- Flash Loader, Add Device: Choose the device that is going to program the flash
- SOF Data, Add Sof Page: add the .sof file generate during the synthesis
- Generate
Flashing
Now you're ready for flashing, go to the Programmer in Quartus II, and since a movie is worth a thousand words, I made a how-to video, download and follow the steps:
# Set the correct configuration to UNKNOWN devices in the JTAG chain.
- In this case, the unknown devices are buffers for the VME bus:
## Double click on the UNKNOWN_XXXX
## Device family-> User Defined
## Edit->
** Device name e.g BUFFER_VME
** Intruction Register e.g 8
- Add a programming file to the Device EP2AGX125, the FPGA.
- Attach Flash Device to the FPGA, EPCS128
- Click on "Program/Configure" for the FPGA, and "Examine" for the Flash
- Add the jic file to the Flash.
- Click on Program/Configure for the Flash.
The SPI Flash after this should be programmed, please let me know if you have any problem (c.prados@gsi.de).