There are three functions with the same name.
This commit writes a different name for each function.

If the address input of the function is std_logic_vector the function name is not renamed.

If the address input of the function is std_ulogic_vector the function name is renamed to:
address_trans_u

If the address input of the function is bit_vector the function name is renamed to:
address_trans_b

See wr-cores#101 for more info

This is because since the VHDL 2008 standard the word “default” is a reserved word.

See wr-cores#101 for more info

Resolve "release v3.1.2"

Closes #5

See merge request be-cem-edl/common/gn4124-core!4

Resolve "simplify l2p_dma_master fifo reset logic"

Closes #4

See merge request be-cem-edl/common/gn4124-core!3

Resolve "Timing issues related to l2p_arbiter outputs"

Closes #3

See merge request be-cem-edl/common/gn4124-core!2

See also #3

Fix component, create release

See merge request be-cem-edl/common/gn4124-core!1

Also fix some typos.

Remove unused signals, renaming.

And refactoring.

3.0.1 - 2020-09-29
==================
https://www.ohwr.org/project/gn4124-core/tree/v3.0.1

Fixed
-----
- hdl: L2P DMA issues reported with slower hosts

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

The FIFO size and full threshold need to be enough to hold if necessary all the pending read data
requests from the WB slave.

In the case of the Spartan-6 DDR controller being the WB slave, the FIFO needs to be able to store
up to 192 words (128 from the controller itself, plus 64 from our wrapper).

Since the GN4124 is used primarily on the SPEC, this is now the default value for the L2P DMA
master.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This bug was not affecting the design, as it would read once from an empty FIFO only after
the transfer was done.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This commit fixes an issue that would cause the L2P DMA to drop some data when the WB slave would
stall at the same cycle as the dual-clock FIFO would raise the 'full' flag.

The WB state machine has been redesigned in order to solve this issue and make sure that data is
properly retained when this condition appears.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>