Fix bugs in DMA wishbone masters.

Modify CSR wishbone address map, BAR0 + BAR2.
Fix bug with LED.
Fix bug wb slave clk is wb clk not core clk.

Add clock input on wb bus of the core's top entity.

Lots of clean up in comments and layout.

Check L2P channel status when sending data to GN4124.

Work on abort feature in dma masters.

Always write data to csr wb bus even for rd cycles => timing optimisation.

Fix a bug in packet length testing.

Change data from decoder latching in wbmaster32.

Work on p2l_decoder32.

Change dma_controller slave wishbone address.

Put byte swapping in a function.
Modify wbmaster entity (remove gn4124_clk_i, add wb_clk_i, add wb_stall_i).

Clean up commented code.
Add more comments.

Add a wb_clk.
Allow a granted source to request access, in arbiter.

Remove dead time in wb slave simuator (counter).