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Commit 8735df15 authored by Matthieu Cattin's avatar Matthieu Cattin
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Implement DMA abort. 

Check L2P channel status when sending data to GN4124.
parent add2b142
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hdl/gn4124core/dma_controller.vhd
+ 7
− 3
View file @ 8735df15
......@@ -21,7 +21,7 @@
--------------------------------------------------------------------------------
-- last changes: 30-09-2010 (mcattin) Add status, error and abort
--------------------------------------------------------------------------------
-- TODO: - Abort feature
-- TODO:
--
--------------------------------------------------------------------------------
......@@ -41,7 +41,7 @@ entity dma_controller is
---------------------------------------------------------
-- Interrupt request
dma_ctrl_irq_o : out std_logic;
dma_ctrl_irq_o : out std_logic_vector(1 downto 0);
---------------------------------------------------------
-- To the L2P DMA master and P2L DMA master
......@@ -313,8 +313,12 @@ begin
dma_ctrl_byte_swap_o <= dma_ctrl_reg(3 downto 2);
------------------------------------------------------------------------------
-- IRQ output assignement
------------------------------------------------------------------------------
dma_ctrl_irq_o <= dma_error_irq & dma_done_irq;
------------------------------------------------------------------------------
-- DMA controller FSM
------------------------------------------------------------------------------
p_fsm : process (sys_clk_i, sys_rst_n_i)
......
hdl/gn4124core/gn4124_core.vhd
+ 121
− 111
View file @ 8735df15
......@@ -6,7 +6,8 @@
--
-- unit name: Gn4124 core main block (gn4124-core.vhd)
--
-- authors: Simon Deprez (simon.deprez@cern.ch)
-- Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 31-08-2010
--
......@@ -18,11 +19,9 @@
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes: <date> <initials> <log>
-- <extended description>
-- last changes: 23-09-2010 (mcattin)
--------------------------------------------------------------------------------
-- TODO: - P2L DMA master
-- - Interrupt
-- TODO: -
-- -
--------------------------------------------------------------------------------
......@@ -60,9 +59,10 @@ entity gn4124_core is
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_o : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
---------------------------------------------------------
-- L2P Direction
......@@ -79,12 +79,11 @@ entity gn4124_core is
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic : -- Interrupt request pulse from IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
......@@ -97,7 +96,6 @@ entity gn4124_core is
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_ack_i : in std_logic;
--wb_stall_i : in std_logic;
---------------------------------------------------------
-- DMA interface (Pipelined wishbone master)
......@@ -113,6 +111,7 @@ entity gn4124_core is
);
end gn4124_core;
--==============================================================================
-- Architecture declaration for GN4124 core (gn4124_core)
--==============================================================================
......@@ -135,17 +134,21 @@ architecture rtl of gn4124_core is
signal rst_reg : std_logic;
signal rst_n : std_logic;
-------------------------------------------------------------
-- P2L DataPath (from deserializer to packet decoder)
-------------------------------------------------------------
-------------------------------------------------------------
-- P2L DataPath (from deserializer to packet decoder)
-------------------------------------------------------------
signal des_pd_valid : std_logic;
signal des_pd_dframe : std_logic;
signal des_pd_data : std_logic_vector(31 downto 0);
-------------------------------------------------------------
-- P2L DataPath (from packet decoder to Wishbone master and P2L DMA master)
-------------------------------------------------------------
-- Local bus control
signal p_wr_rdy : std_logic;
signal p2l_rdy_wbm : std_logic;
signal p2l_rdy_pdm : std_logic;
-------------------------------------------------------------
-- P2L DataPath (from packet decoder to Wishbone master and P2L DMA master)
-------------------------------------------------------------
signal p2l_hdr_start : std_logic; -- Indicates Header start cycle
signal p2l_hdr_length : std_logic_vector(9 downto 0); -- Latched LENGTH value from header
signal p2l_hdr_cid : std_logic_vector(1 downto 0); -- Completion ID
......@@ -163,10 +166,6 @@ architecture rtl of gn4124_core is
signal p2l_addr : std_logic_vector(31 downto 0); -- Registered and counting Address
signal p2l_addr_start : std_logic;
signal p_wr_rdy : std_logic;
signal p2l_rdy_wbm : std_logic;
signal p2l_rdy_pdm : std_logic;
-------------------------------------------------------------
-- L2P DataPath (from arbiter to serializer)
-------------------------------------------------------------
......@@ -174,15 +173,16 @@ architecture rtl of gn4124_core is
signal arb_ser_dframe : std_logic;
signal arb_ser_data : std_logic_vector(31 downto 0);
signal l2p_data_o_o : std_logic_vector(l2p_data_o'range);
-- Resync bridge controls
signal Il_wr_rdy_i : std_logic; -- Clocked version of L_WR_RDY from GN412x
signal Ip_rd_d_rdy_i : std_logic; -- Clocked version of p_rd_d_rdy_i from GN412x
signal Il2p_rdy_i : std_logic; -- Clocked version of l2p_rdy_i from GN412x
-- Local bus control
signal l_wr_rdy_t : std_logic_vector(1 downto 0);
signal l_wr_rdy : std_logic_vector(1 downto 0);
signal p_rd_d_rdy_t : std_logic_vector(1 downto 0);
signal p_rd_d_rdy : std_logic_vector(1 downto 0);
signal l2p_rdy_t : std_logic;
signal l2p_rdy : std_logic;
-------------------------------------------------------------
-- Target Controller (Wishbone master)
-- CSR wishbone master to arbiter
-------------------------------------------------------------
signal wbm_arb_valid : std_logic;
signal wbm_arb_dframe : std_logic;
......@@ -190,6 +190,24 @@ architecture rtl of gn4124_core is
signal wbm_arb_req : std_logic;
signal arb_wbm_gnt : std_logic;
-------------------------------------------------------------
-- L2P DMA master to arbiter
-------------------------------------------------------------
signal ldm_arb_req : std_logic; -- Request use of the L2P bus
signal arb_ldm_gnt : std_logic; -- L2P bus emits data on behalf of the L2P DMA
signal ldm_arb_valid : std_logic;
signal ldm_arb_dframe : std_logic;
signal ldm_arb_data : std_logic_vector(31 downto 0);
-------------------------------------------------------------
-- P2L DMA master to arbiter
-------------------------------------------------------------
signal pdm_arb_valid : std_logic;
signal pdm_arb_dframe : std_logic;
signal pdm_arb_data : std_logic_vector(31 downto 0);
signal pdm_arb_req : std_logic;
signal arb_pdm_gnt : std_logic;
-------------------------------------------------------------
-- DMA controller
-------------------------------------------------------------
......@@ -219,6 +237,9 @@ architecture rtl of gn4124_core is
signal next_item_attrib : std_logic_vector(31 downto 0);
signal next_item_valid : std_logic;
------------------------------------------------------------------------------
-- CSR wishbone bus
------------------------------------------------------------------------------
signal wb_adr : std_logic_vector(31 downto 0); -- Adress
signal wb_dat_s2m : std_logic_vector(31 downto 0); -- Data in
signal wb_dat_m2s : std_logic_vector(31 downto 0); -- Data out
......@@ -229,9 +250,11 @@ architecture rtl of gn4124_core is
signal wb_ack : std_logic; -- Acknowledge
signal wb_stall : std_logic; -- Pipelined mode
signal wb_ack_dma_ctrl : std_logic; --
--signal wb_stall_dma_ctrl : std_logic; --
signal wb_dat_s2m_dma_ctrl : std_logic_vector(31 downto 0); --
------------------------------------------------------------------------------
-- DMA wishbone bus
------------------------------------------------------------------------------
signal l2p_dma_adr : std_logic_vector(31 downto 0); -- Adress
signal l2p_dma_dat_s2m : std_logic_vector(31 downto 0); -- Data in
signal l2p_dma_dat_m2s : std_logic_vector(31 downto 0); -- Data out
......@@ -252,25 +275,6 @@ architecture rtl of gn4124_core is
signal p2l_dma_ack : std_logic; -- Acknowledge
signal p2l_dma_stall : std_logic; -- Acknowledge
-------------------------------------------------------------
-- L2P DMA master
-------------------------------------------------------------
signal ldm_arb_req : std_logic; -- Request use of the L2P bus
signal arb_ldm_gnt : std_logic; -- L2P bus emits data on behalf of the L2P DMA
signal ldm_arb_valid : std_logic;
signal ldm_arb_dframe : std_logic;
signal ldm_arb_data : std_logic_vector(31 downto 0);
-- signal IL2P_DMA_RDY : STD_LOGIC; -- Clocked version of l2p_rdy_i from GN412x
-------------------------------------------------------------
-- P2L DMA master
-------------------------------------------------------------
signal pdm_arb_valid : std_logic;
signal pdm_arb_dframe : std_logic;
signal pdm_arb_data : std_logic_vector(31 downto 0);
signal pdm_arb_req : std_logic;
signal arb_pdm_gnt : std_logic;
--==============================================================================
-- Architecture begin (gn4124_core)
......@@ -318,7 +322,6 @@ begin
end if;
end process;
cmp_rst_buf : BUFG
port map (
I => rst_reg,
......@@ -332,9 +335,9 @@ begin
--=============================================================================================--
--=============================================================================================--
-----------------------------------------------------------------------------
-- p2l_des: Deserialize the P2L DDR inputs
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- p2l_des: Deserialize the P2L DDR inputs
-----------------------------------------------------------------------------
cmp_p2l_des : p2l_des
port map
(
......@@ -361,9 +364,15 @@ begin
p2l_data_o => des_pd_data
);
-----------------------------------------------------------------------------
-- p2l_decode32: Decode the output of the p2l_des
-----------------------------------------------------------------------------
------------------------------------------------------------------------------
-- P2L local bus control signals
------------------------------------------------------------------------------
-- de-asserted to pause transfer from GN4124
p2l_rdy_o <= p2l_rdy_wbm and p2l_rdy_pdm;
-----------------------------------------------------------------------------
-- p2l_decode32: Decode the output of the p2l_des
-----------------------------------------------------------------------------
cmp_p2l_decode32 : p2l_decode32
port map
(
......@@ -405,32 +414,15 @@ begin
);
-----------------------------------------------------------------------------
-- Resync some GN412x Signals
-----------------------------------------------------------------------------
process (clk_p, rst_n)
begin
if(rst_n = c_RST_ACTIVE) then
Il_wr_rdy_i <= '0';
Ip_rd_d_rdy_i <= '0';
Il2p_rdy_i <= '0';
elsif rising_edge(clk_p) then
Il_wr_rdy_i <= l_wr_rdy_i(0);
Ip_rd_d_rdy_i <= p_rd_d_rdy_i(0);
Il2p_rdy_i <= l2p_rdy_i;
end if;
end process;
--=============================================================================================--
--=============================================================================================--
--== Core Logic Blocks
--=============================================================================================--
--=============================================================================================--
-----------------------------------------------------------------------------
-- Wishbone master
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Wishbone master
-----------------------------------------------------------------------------
u_wbmaster32 : wbmaster32
generic map
(
......@@ -467,8 +459,9 @@ begin
---------------------------------------------------------
-- P2L Control
p_wr_rdy_o => p_wr_rdy,
p2l_rdy_o => p2l_rdy_wbm,
p_wr_rdy_o => p_wr_rdy_o,
p2l_rdy_o => p2l_rdy_wbm,
p_rd_d_rdy_i => p_rd_d_rdy,
---------------------------------------------------------
-- To the L2P Interface
......@@ -500,16 +493,14 @@ begin
wb_stb_o <= wb_stb;
wb_we_o <= wb_we;
wb_ack <= wb_ack_i or wb_ack_dma_ctrl;
--wb_stall <= wb_stall_i or wb_stall_dma_ctrl;
--wb_stall_dma_ctrl <= wb_stb and not wb_ack;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- DMA controller
-----------------------------------------------------------------------------
u_dma_controller : dma_controller
-----------------------------------------------------------------------------
port map
(
--DEBUG=> LED (7 downto 4),
sys_clk_i => clk_p, --sys_clk_i,
sys_clk_i => clk_p,
sys_rst_n_i => rst_n,
dma_ctrl_irq_o => dma_irq_o,
......@@ -545,16 +536,17 @@ begin
wb_ack_o => wb_ack_dma_ctrl
);
-- Status signals from DMA masters
dma_ctrl_done <= dma_ctrl_l2p_done or dma_ctrl_p2l_done;
dma_ctrl_error <= dma_ctrl_l2p_error or dma_ctrl_p2l_error;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- L2P DMA master
-----------------------------------------------------------------------------
u_l2p_dma_master : l2p_dma_master
-----------------------------------------------------------------------------
port map
(
sys_clk_i => clk_p, --sys_clk_i,
sys_clk_i => clk_p,
sys_rst_n_i => rst_n,
dma_ctrl_target_addr_i => dma_ctrl_carrier_addr,
......@@ -573,6 +565,10 @@ begin
ldm_arb_req_o => ldm_arb_req,
arb_ldm_gnt_i => arb_ldm_gnt,
l2p_edb_o => l2p_edb_o,
l_wr_rdy_i => l_wr_rdy,
l2p_rdy_i => l2p_rdy,
l2p_dma_clk_i => clk_p,
l2p_dma_adr_o => l2p_dma_adr,
l2p_dma_dat_i => l2p_dma_dat_s2m,
......@@ -585,13 +581,13 @@ begin
l2p_dma_stall_i => l2p_dma_stall
);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- P2L DMA master
-----------------------------------------------------------------------------
u_p2l_dma_master : p2l_dma_master
-----------------------------------------------------------------------------
port map
(
DEBUG => LED (7 downto 4),
sys_clk_i => clk_p, --sys_clk_i,
sys_clk_i => clk_p,
sys_rst_n_i => rst_n,
dma_ctrl_carrier_addr_i => dma_ctrl_carrier_addr,
......@@ -616,7 +612,8 @@ begin
pd_pdm_data_i => p2l_d,
pd_pdm_be_i => p2l_be,
p2l_rdy_o => p2l_rdy_pdm,
p2l_rdy_o => p2l_rdy_pdm,
rx_error_o => rx_error_o,
pdm_arb_valid_o => pdm_arb_valid,
pdm_arb_dframe_o => pdm_arb_dframe,
......@@ -659,29 +656,42 @@ begin
p2l_dma_stall <= dma_stall_i;
-----------------------------------------------------------------------------
-- Top Level LB Controls
-----------------------------------------------------------------------------
p_wr_rdy_o <= p_wr_rdy & p_wr_rdy; -- assert when wbmaster32 ready to receive target write
rx_error_o <= '0'; -- assert when p2l dma master aborted
l2p_edb_o <= '0'; -- assert when l2p dma master aborted
-- de-asserted to pause transfer from GN4124
p2l_rdy_o <= p2l_rdy_wbm and p2l_rdy_pdm;
--=============================================================================================--
--=============================================================================================--
--== L2P DataPath
--=============================================================================================--
--=============================================================================================--
-----------------------------------------------------------------------------
-- ARBITER: Arbitrate between Wishbone master, DMA master and DMA pdmuencer
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Resync GN412x L2P status signals
-----------------------------------------------------------------------------
process (clk_p, rst_n)
begin
if(rst_n = c_RST_ACTIVE) then
l_wr_rdy_t <= "00";
l_wr_rdy <= "00";
p_rd_d_rdy_t <= "00";
p_rd_d_rdy <= "00";
l2p_rdy_t <= '0';
l2p_rdy <= '0';
elsif rising_edge(clk_p) then
-- must be checked before l2p_dma_master issues a master write
l_wr_rdy_t <= l_wr_rdy_i;
l_wr_rdy <= l_wr_rdy_t;
-- must be checked before wbmaster32 sends read completion with data
p_rd_d_rdy_t <= p_rd_d_rdy_i;
p_rd_d_rdy <= p_rd_d_rdy_t;
-- when de-asserted, l2p_dma_master must stop sending data (de-assert l2p_valid) within 3 (or 7 ?) clock cycles
l2p_rdy_t <= l2p_rdy_i;
l2p_rdy <= l2p_rdy_t;
end if;
end process;
-----------------------------------------------------------------------------
-- L2P arbiter, arbitrates access to GN4124
-----------------------------------------------------------------------------
u_arbiter : arbiter
port map
(
......@@ -723,9 +733,9 @@ begin
-----------------------------------------------------------------------------
-- L2P_SER: Generate the L2P DDR Outputs
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- L2P_SER: Generate the L2P DDR Outputs
-----------------------------------------------------------------------------
cmp_l2p_ser : l2p_ser
port map
(
......
hdl/gn4124core/gn4124_core_pkg.vhd
+ 11
− 5
View file @ 8735df15
......@@ -176,8 +176,9 @@ package gn4124_core_pkg is
---------------------------------------------------------
-- P2L Control
p_wr_rdy_o : out std_logic; -- Write buffer not empty
p2l_rdy_o : out std_logic; -- Asserted to pause transfer already in progress
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- Ready to accept target write
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- Asserted when GN4124 ready to accept read completion with data
---------------------------------------------------------
-- To the L2P Interface
......@@ -288,6 +289,12 @@ package gn4124_core_pkg is
ldm_arb_req_o : out std_logic;
arb_ldm_gnt_i : in std_logic;
---------------------------------------------------------
-- L2P channel control
l2p_edb_o : out std_logic; -- Asserted when transfer is aborted
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Asserted when GN4124 is ready to receive master write
l2p_rdy_i : in std_logic; -- De-asserted to pause transfer already in progress
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
l2p_dma_clk_i : in std_logic; -- Bus clock
......@@ -308,8 +315,6 @@ package gn4124_core_pkg is
-----------------------------------------------------------------------------
port
(
DEBUG : out std_logic_vector(3 downto 0);
---------------------------------------------------------
-- Clock/Reset
sys_clk_i : in std_logic;
......@@ -346,7 +351,8 @@ package gn4124_core_pkg is
---------------------------------------------------------
-- P2L control
p2l_rdy_o : out std_logic; -- Asserted to pause transfer already in progress
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
rx_error_o : out std_logic; -- Asserted when transfer is aborted
---------------------------------------------------------
-- To the L2P Interface (send the DMA Master Read request)
......
hdl/gn4124core/l2p_dma_master.vhd
+ 30
− 5
View file @ 8735df15
......@@ -24,7 +24,6 @@
-- Dead times optimisation in packet generator.
--------------------------------------------------------------------------------
-- TODO: - issue an error if ask DMA transfert of length = 0
-- - Abort feature => assert L2P_EDB (EnD of packet Bad)
--------------------------------------------------------------------------------
library IEEE;
......@@ -65,6 +64,12 @@ entity l2p_dma_master is
ldm_arb_req_o : out std_logic;
arb_ldm_gnt_i : in std_logic;
---------------------------------------------------------
-- L2P channel control
l2p_edb_o : out std_logic; -- Asserted when transfer is aborted
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Asserted when GN4124 is ready to receive master write
l2p_rdy_i : in std_logic; -- De-asserted to pause transfer already in progress
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
l2p_dma_clk_i : in std_logic; -- Bus clock
......@@ -157,7 +162,8 @@ architecture behaviour of l2p_dma_master is
signal wb_ack_cnt : unsigned(6 downto 0);
-- L2P DMA Master FSM
type l2p_dma_state_type is (L2P_IDLE, L2P_WAIT_DATA, L2P_HEADER, L2P_ADDR_H, L2P_ADDR_L, L2P_DATA, L2P_LAST_DATA);
type l2p_dma_state_type is (L2P_IDLE, L2P_WAIT_DATA, L2P_HEADER, L2P_ADDR_H,
L2P_ADDR_L, L2P_DATA, L2P_LAST_DATA, L2P_WAIT_RDY);
signal l2p_dma_current_state : l2p_dma_state_type;
-- L2P packet generator
......@@ -334,6 +340,7 @@ begin
ldm_arb_dframe_o <= '0';
data_fifo_rd <= '0';
dma_ctrl_done_o <= '0';
l2p_edb_o <= '0';
elsif rising_edge(sys_clk_i) then
case l2p_dma_current_state is
......@@ -344,8 +351,9 @@ begin
ldm_arb_data_o <= (others => '0');
ldm_arb_valid_o <= '0';
ldm_arb_dframe_o <= '0';
l2p_edb_o <= '0';
if (data_fifo_empty = '0') then
if (data_fifo_empty = '0' and l_wr_rdy_i = "11") then
-- We have data to send -> prepare a packet, first the header
l2p_dma_current_state <= L2P_HEADER;
-- request access to PCIe bus
......@@ -400,14 +408,31 @@ begin
-- send data with byte swap if requested
ldm_arb_data_o <= f_byte_swap(g_BYTE_SWAP, data_fifo_dout, l2p_byte_swap);
ldm_arb_valid_o <= '1';
-- data not ready yet, wait for it
if(data_fifo_empty = '1') then
if (dma_ctrl_abort_i = '1') then
l2p_edb_o <= '1';
l2p_dma_current_state <= L2P_IDLE;
elsif(data_fifo_empty = '1') then
-- data not ready yet, wait for it
l2p_dma_current_state <= L2P_WAIT_DATA;
elsif(l2p_data_cnt <= 2) then
-- Only one 32-bit data word to send
l2p_dma_current_state <= L2P_LAST_DATA;
-- Stop reading from fifo
data_fifo_rd <= '0';
elsif (l2p_rdy_i = '0') then
-- GN4124 not able to receive more data, have to wait
l2p_dma_current_state <= L2P_WAIT_RDY;
-- Stop reading from fifo
data_fifo_rd <= '0';
end if;
when L2P_WAIT_RDY =>
ldm_arb_valid_o <= '0';
if (l2p_rdy_i = '1') then
-- GN4124 is ready to receive more data
l2p_dma_current_state <= L2P_DATA;
-- Re-start fifo reading
data_fifo_rd <= '1';
end if;
when L2P_WAIT_DATA =>
......
hdl/gn4124core/lotus.vhd
+ 3
− 3
View file @ 8735df15
......@@ -181,7 +181,7 @@ architecture BEHAVIOUR of LOTUS is
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_o : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
......@@ -205,7 +205,7 @@ architecture BEHAVIOUR of LOTUS is
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic : -- Interrupt request pulse from IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
......@@ -332,7 +332,7 @@ begin
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_o => P_WR_REQ,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
......
hdl/gn4124core/p2l_dma_master.vhd
+ 9
− 6
View file @ 8735df15
......@@ -25,7 +25,7 @@
--------------------------------------------------------------------------------
-- TODO: - byte swap
-- - byte enable support.
-- - abort feature => assert RX_ERROR to GN4124
-- - issue an error if ask DMA transfert of length = 0
--------------------------------------------------------------------------------
library IEEE;
......@@ -37,9 +37,6 @@ use work.gn4124_core_pkg.all;
entity p2l_dma_master is
port
(
DEBUG : out std_logic_vector(3 downto 0);
---------------------------------------------------------
-- Clock/Reset
sys_clk_i : in std_logic;
......@@ -76,7 +73,8 @@ entity p2l_dma_master is
---------------------------------------------------------
-- P2L control
p2l_rdy_o : out std_logic; -- Asserted to pause transfer already in progress
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
rx_error_o : out std_logic; -- Asserted when transfer is aborted
---------------------------------------------------------
-- To the P2L Interface (send the DMA Master Read request)
......@@ -276,6 +274,7 @@ begin
dma_ctrl_done_o <= '0';
next_item_valid_o <= '0';
completion_error <= '0';
rx_error_o <= '0';
elsif rising_edge(sys_clk_i) then
case p2l_dma_current_state is
......@@ -284,6 +283,7 @@ begin
dma_ctrl_done_o <= '0';
next_item_valid_o <= '0';
completion_error <= '0';
rx_error_o <= '0';
-- Start a read request when a P2L DMA is initated or when the DMA
-- controller asks for the next DMA info (in a chained DMA).
if (dma_ctrl_start_p2l_i = '1' or dma_ctrl_start_next_i = '1') then
......@@ -327,7 +327,10 @@ begin
when P2L_WAIT_READ_COMPLETION =>
-- End of the read request packet
pdm_arb_valid_o <= '0';
if (pd_pdm_master_cpld_i = '1' and pd_pdm_data_last_i = '1') then
if (dma_ctrl_abort_i = '1') then
rx_error_o <= '1';
p2l_dma_current_state <= P2L_IDLE;
elsif (pd_pdm_master_cpld_i = '1' and pd_pdm_data_last_i = '1') then
-- last word of read completion has been received
if (l2p_last_packet = '0') then
-- A new read request is needed, DMA size > max payload
......
hdl/gn4124core/wbmaster32.vhd
+ 6
− 5
View file @ 8735df15
......@@ -24,7 +24,6 @@
-- Dead times optimisation in packet generator.
--------------------------------------------------------------------------------
-- TODO: - byte enable support.
-- -
--------------------------------------------------------------------------------
library IEEE;
......@@ -70,8 +69,9 @@ entity wbmaster32 is
---------------------------------------------------------
-- P2L channel control
p_wr_rdy_o : out std_logic; -- Ready to accept target write
p2l_rdy_o : out std_logic; -- Asserted to pause transfer already in progress
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- Ready to accept target write
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- Asserted when GN4124 ready to accept read completion with data
---------------------------------------------------------
-- To the arbiter (L2P data)
......@@ -163,7 +163,7 @@ begin
------------------------------------------------------------------------------
-- ready to receive new target write if fifo not full
p_wr_rdy_o <= not(to_wb_fifo_full);
p_wr_rdy_o <= "00" when to_wb_fifo_full = '1' else "11";
-- pause transfer from GN4124 when fifo is full
p2l_rdy_o <= not(to_wb_fifo_full);
......@@ -243,7 +243,8 @@ begin
wbm_arb_data_o <= (others => '0');
wbm_arb_valid_o <= '0';
wbm_arb_dframe_o <= '0';
if(from_wb_fifo_empty = '0') then
if(from_wb_fifo_empty = '0' and p_rd_d_rdy_i = "11") then
-- generate a packet when read data in fifo and GN4124 ready to receive the packet
wbm_arb_req_o <= '1';
from_wb_fifo_rd <= '1';
l2p_read_cpl_current_state <= L2P_HEADER;
......
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