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Commit 1a42e8c8 authored by Matthieu Cattin's avatar Matthieu Cattin
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Re-organize and rename files, entities and components.

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hdl/gn4124core/ddr_out.vhd deleted 100644 → 0
+ 0
− 92
View file @ 74abe83c
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: DDR_OUT (ddr_out.vhd)
--
-- author:
--
-- date:
--
-- version: 0.1
--
-- description: Generic technology dependent DDR output for Xilinx.
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes: <date> <initials> <log>
-- <extended description>
--------------------------------------------------------------------------------
-- TODO: -
-- -
-- -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity DDR_OUT is
generic
(
WIDTH : integer := 20
);
port
(
-- Reset
RESET : in std_ulogic;
-- Clock
CLKp : in std_ulogic;
CLKn : in std_ulogic;
-- Clock Enable
CE : in std_ulogic;
-- Input Data
Dp : in std_ulogic_vector(WIDTH-1 downto 0);
Dn : in std_ulogic_vector(WIDTH-1 downto 0);
-- Output Data
Q : out std_ulogic_vector(WIDTH-1 downto 0)
);
end DDR_OUT;
architecture BEHAVIOUR of DDR_OUT is
--component OFDDRRSE
-- port(
-- Q : out std_ulogic;
-- C0 : in std_ulogic;
-- C1 : in std_ulogic;
-- CE : in std_ulogic;
-- D0 : in std_ulogic;
-- D1 : in std_ulogic;
-- R : in std_ulogic;
-- S : in std_ulogic
-- );
--end component; --OFDDRRSE
begin
DDROUT : for i in 0 to WIDTH-1 generate
U : OFDDRRSE
port map
(
Q => Q(i),
C0 => CLKn,
C1 => CLKp,
CE => CE,
D0 => Dn(i),
D1 => Dp(i),
R => RESET,
S => '0'
);
end generate;
end BEHAVIOUR;
hdl/gn4124core/design/gullwing.ucf 0 → 100644
+ 559
− 0
View file @ 1a42e8c8
#---------------------------------------------------------------------------------------------
# IO standards
#---------------------------------------------------------------------------------------------
NET "l2p_data[0]" IOSTANDARD = SSTL18_I;
NET "l2p_data[10]" IOSTANDARD = SSTL18_I;
NET "l2p_data[11]" IOSTANDARD = SSTL18_I;
NET "l2p_data[12]" IOSTANDARD = SSTL18_I;
NET "l2p_data[13]" IOSTANDARD = SSTL18_I;
NET "l2p_data[14]" IOSTANDARD = SSTL18_I;
NET "l2p_data[15]" IOSTANDARD = SSTL18_I;
NET "l2p_data[1]" IOSTANDARD = SSTL18_I;
NET "l2p_data[2]" IOSTANDARD = SSTL18_I;
NET "l2p_data[3]" IOSTANDARD = SSTL18_I;
NET "l2p_data[4]" IOSTANDARD = SSTL18_I;
NET "l2p_data[5]" IOSTANDARD = SSTL18_I;
NET "l2p_data[6]" IOSTANDARD = SSTL18_I;
NET "l2p_data[7]" IOSTANDARD = SSTL18_I;
NET "l2p_data[8]" IOSTANDARD = SSTL18_I;
NET "l2p_data[9]" IOSTANDARD = SSTL18_I;
NET "l2p_clkp" IOSTANDARD = DIFF_SSTL18_I;
NET "l2p_clkn" IOSTANDARD = DIFF_SSTL18_I;
NET "l2p_rdy" IOSTANDARD = SSTL18_I;
NET "l_clkn" IOSTANDARD = DIFF_SSTL18_I; #SSTL18_I;
NET "l_clkp" IOSTANDARD = DIFF_SSTL18_I; #SSTL18_I;
NET "l_rst_n" IOSTANDARD = SSTL18_I;
NET "p2l_clkp" IOSTANDARD = DIFF_SSTL18_I;
NET "p2l_clkn" IOSTANDARD = DIFF_SSTL18_I;
NET "p2l_data[0]" IOSTANDARD = SSTL18_I;
NET "p2l_data[10]" IOSTANDARD = SSTL18_I;
NET "p2l_data[11]" IOSTANDARD = SSTL18_I;
NET "p2l_data[12]" IOSTANDARD = SSTL18_I;
NET "p2l_data[13]" IOSTANDARD = SSTL18_I;
NET "p2l_data[14]" IOSTANDARD = SSTL18_I;
NET "p2l_data[15]" IOSTANDARD = SSTL18_I;
NET "p2l_data[1]" IOSTANDARD = SSTL18_I;
NET "p2l_data[2]" IOSTANDARD = SSTL18_I;
NET "p2l_data[3]" IOSTANDARD = SSTL18_I;
NET "p2l_data[4]" IOSTANDARD = SSTL18_I;
NET "p2l_data[5]" IOSTANDARD = SSTL18_I;
NET "p2l_data[6]" IOSTANDARD = SSTL18_I;
NET "p2l_data[7]" IOSTANDARD = SSTL18_I;
NET "p2l_data[8]" IOSTANDARD = SSTL18_I;
NET "p2l_data[9]" IOSTANDARD = SSTL18_I;
NET "p2l_rdy" IOSTANDARD = SSTL18_I;
NET "l_wr_rdy[0]" IOSTANDARD = SSTL18_I;
NET "l_wr_rdy[1]" IOSTANDARD = SSTL18_I;
NET "p_rd_d_rdy[0]" IOSTANDARD = SSTL18_I;
NET "p_rd_d_rdy[1]" IOSTANDARD = SSTL18_I;
NET "l2p_dframe" IOSTANDARD = SSTL18_I;
NET "l2p_valid" IOSTANDARD = SSTL18_I;
NET "l2p_edb" IOSTANDARD = SSTL18_I;
NET "p2l_dframe" IOSTANDARD = SSTL18_I;
NET "p2l_valid" IOSTANDARD = SSTL18_I;
NET "p_wr_rdy[0]" IOSTANDARD = SSTL18_I;
NET "p_wr_rdy[1]" IOSTANDARD = SSTL18_I;
NET "rx_error" IOSTANDARD = SSTL18_I;
NET "tx_error" IOSTANDARD = SSTL18_I;
NET "vc_rdy[0]" IOSTANDARD = SSTL18_I;
NET "vc_rdy[1]" IOSTANDARD = SSTL18_I;
NET "p_wr_req[0]" IOSTANDARD = SSTL18_I;
NET "p_wr_req[1]" IOSTANDARD = SSTL18_I;
NET "l_rst33_n" IOSTANDARD = "LVCMOS33";
## GN1559 de-serializer
NET "des[*]" IOSTANDARD = "LVCMOS33";
NET "des_pclk" IOSTANDARD = "LVCMOS33";
## GN1531 serializer
NET "ser[*]" IOSTANDARD = "LVCMOS33";
## GN1559 related
NET "des_h" IOSTANDARD = "LVCMOS33";
NET "des_v" IOSTANDARD = "LVCMOS33";
NET "des_f" IOSTANDARD = "LVCMOS33";
NET "des_smpte_bypass" IOSTANDARD = "LVCMOS33";
NET "des_dvb_asi" IOSTANDARD = "LVCMOS33";
NET "des_sdhdn" IOSTANDARD = "LVCMOS33";
## GN1531 related
NET "ser_h" IOSTANDARD = "LVCMOS33";
NET "ser_v" IOSTANDARD = "LVCMOS33";
NET "ser_f" IOSTANDARD = "LVCMOS33";
NET "ser_smpte_bypass" IOSTANDARD = "LVCMOS33";
NET "ser_dvb_asi" IOSTANDARD = "LVCMOS33";
NET "ser_sdhdn" IOSTANDARD = "LVCMOS33";
## GN4911 Timing Generator
NET "syncseperator_h_timing" IOSTANDARD = "LVCMOS33";
NET "syncseperator_v_timing" IOSTANDARD = "LVCMOS33";
NET "syncseperator_f_timing" IOSTANDARD = "LVCMOS33";
# GPIO
NET "gpio[*]" IOSTANDARD = "LVCMOS33";
# I2C
NET "sda" IOSTANDARD = "LVCMOS33";
NET "scl" IOSTANDARD = "LVCMOS33";
# MICTOR connector
NET "mic_clka" IOSTANDARD = "LVCMOS33";
NET "mic_clkb" IOSTANDARD = "LVCMOS33";
NET "mic_data[*]" IOSTANDARD = "LVCMOS33";
# debug input switches
NET "debug[*]" IOSTANDARD = "LVCMOS33";
NET "led[*]" IOSTANDARD = "LVCMOS33";
NET "spi_sck" IOSTANDARD = "LVCMOS33";
NET "spi_ss[*]" IOSTANDARD = "LVCMOS33";
NET "spi_mosi" IOSTANDARD = "LVCMOS33";
NET "spi_miso" IOSTANDARD = "LVCMOS33";
NET "gs4911_host_b" IOSTANDARD = "LVCMOS33";
NET "gs4911_sclk" IOSTANDARD = "LVCMOS33";
NET "gs4911_sdin" IOSTANDARD = "LVCMOS33";
NET "gs4911_sdout" IOSTANDARD = "LVCMOS33";
NET "gs4911_csb" IOSTANDARD = "LVCMOS33";
NET "PCLK_4911_1531" IOSTANDARD = "LVCMOS33";
NET "GS4911_LOCK_LOST" IOSTANDARD = "LVCMOS33";
NET "GS4911_REF_LOST" IOSTANDARD = "LVCMOS33";
#---------------------------------------------------------------------------------------------
# Force DDR Flops into IOBs
# Offset constraints shoudl force this although the input and output DDR primtives are
# instantiated within the RTL.
#---------------------------------------------------------------------------------------------
#INST "lp2_data<*>" IOB=TRUE;
#INST "l2p_dframe" IOB=TRUE;
#INST "l2p_valid" IOB=TRUE;
#INST "l2p_edb" IOB=TRUE;
#
#---------------------------------------------------------------------------------------------
# Constrain DDR inputs
# Assume offset requirement of 6.25 on inputs for a 10ns clock
#---------------------------------------------------------------------------------------------
# Group the I/O pads -- 0 degree clock
# Create a PERIOD constraint on the original clock
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
#### mcattin ####
#TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 4.8 ns HIGH 50%;
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
#### mcattin ####
#TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 4.8 ns HIGH 50%;
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 5 ns HIGH 50%;
NET "P2L_CLKp" IBUF_DELAY_VALUE= 0;
NET "P2L_CLKn" IBUF_DELAY_VALUE= 0;
# Create an OFFSET constraint for the ddr group
NET "p2l_data*" IFD_DELAY_VALUE = 2; # Option: 0-8 or AUTO(does not work)
net "p2l_data*" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "P2L_CLKp" high;
net "p2l_data*" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "P2L_CLKn" high;
#---------------------------------------------------------------------------------------------
# Constrain DDR outputs
# Assume offset requirement of 7.5 on outputs for a 10ns clock period
#---------------------------------------------------------------------------------------------
# Create an OFFSET constraint for the ddr group
# There is a minimum delay of ~3.2ns from the DDRDFF to the pad!!!!
NET "l2p_data*" OFFSET = OUT 6.5 ns AFTER "P2L_CLKp" high;
NET "l2p_data*" OFFSET = OUT 6.5 ns AFTER "P2L_CLKn" high;
#---------------------------------------------------------------------------------------------
# Constrain the other inputs
#---------------------------------------------------------------------------------------------
NET "p2l_dframe" IFD_DELAY_VALUE = 1; # 0-8 or AUTO
NET "p2l_dframe" OFFSET = IN 1.2 ns VALID 3.0 ns BEFORE "P2L_CLKp" HIGH; ##1.5 ns VALID 2.0 ns
NET "p2l_valid" IFD_DELAY_VALUE = 1;
NET "p2l_valid" OFFSET = IN 1.2 ns VALID 3.0 ns BEFORE "P2L_CLKp" HIGH; ##1.5 ns VALID 2.0 ns
NET "vc_rdy*" maxdelay = 2 ns;
NET "l_wr_rdy*" maxdelay = 2 ns;
NET "p_rd_d_rdy[*]" maxdelay = 2 ns;
NET "l2p_rdy" maxdelay = 2 ns;
#---------------------------------------------------------------------------------------------
# Constrain the other outputs
#---------------------------------------------------------------------------------------------
NET "l2p_dframe" OFFSET = OUT 6.5 ns AFTER "P2L_CLKn" HIGH;
NET "l2p_valid" OFFSET = OUT 6.5 ns AFTER "P2L_CLKn" HIGH;
NET "l2p_clkp" OFFSET = OUT 6.5 ns AFTER "P2L_CLKp" HIGH;
NET "l2p_clkn" OFFSET = OUT 6.5 ns AFTER "P2L_CLKn" HIGH;
#---------------------------------------------------------------------------------------------
# False Path from Aysnchronous reset
#---------------------------------------------------------------------------------------------
NET "l_rst_n" TIG;
##### mcattin #####
#NET "cmp_gn4124_core/cmp_p2l_des/irst*" TIG;
##### mcattin #####
NET "cmp_gn4124_core/rst_*" TIG;
#---------------------------------------------------------------------------------------------
# False Path from write pointer as it is multi cycle
#---------------------------------------------------------------------------------------------
#---------------------------------------------------------------------------------------------
# False Path from all lgogic clocked by l_clk_fpga in tx_fifo to logic clocked by l2p_0_clk
#---------------------------------------------------------------------------------------------
#---------------------------------------------------------------------------------------------
# DCM placement constraints
#---------------------------------------------------------------------------------------------
#INST lbi_0/lt_0/lclk_0/CLK2X_BUFG_INST LOC=BUFGMUX_X1Y0;
##### mcattin #####
#INST cmp_gn4124_core/cmp_p2l_des/iclk_bufg LOC = BUFGMUX_X2Y10;
#INST cmp_gn4124_core/cmp_p2l_des/iclkn_bufg LOC = BUFGMUX_X2Y11;
#NET "P2L_CLKp" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "P2L_CLKn" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "cmp_gn4124_core/cmp_p2l_des/iclk_i" maxdelay = 0.1 ns;
#NET "cmp_gn4124_core/cmp_p2l_des/iclkn_i" maxdelay = 0.1 ns;
##### mcattin #####
#INST cmp_gn4124_core/clk_p_bufg LOC = BUFGMUX_X2Y10;
#INST cmp_gn4124_core/clk_n_bufg LOC = BUFGMUX_X2Y11;
INST cmp_gn4124_core/clk_bufg LOC = BUFGMUX_X2Y10;
INST cmp_gn4124_core/clkn_bufg LOC = BUFGMUX_X2Y11;
NET "P2L_CLKp" CLOCK_DEDICATED_ROUTE = FALSE;
NET "P2L_CLKn" CLOCK_DEDICATED_ROUTE = FALSE;
NET "cmp_gn4124_core/clk_p_buf" maxdelay = 0.1 ns;
NET "cmp_gn4124_core/clk_n_buf" maxdelay = 0.1 ns;
#The IO Location Constraints
NET "des_h" LOC = C10;
NET "gpio[4]" LOC = AB13;
#NET "ser[14]" LOC = A20;
#NET "ddr2_dqs[2]" LOC = K1;
NET "gpio[5]" LOC = AA3;
#NET "ser[15]" LOC = E15;
#NET "cntrl0_ddr2_dqs[3]" LOC = H4;
#NET "cntrl0_ddr2_cs_n" LOC = C1;
NET "gpio[6]" LOC = AA4;
#NET "ser[16]" LOC = F15;
NET "des_v" LOC = G11;
NET "gpio[7]" LOC = AA8;
#NET "ser[17]" LOC = C18;
NET "syncseperator_f_timing" LOC = D7;
NET "p2l_dframe" LOC = L22;
NET "gpio[8]" LOC = V10;
NET "des[10]" LOC = E16;
#NET "ser[18]" LOC = A18;
NET "gpio[9]" LOC = AB2;
NET "des[11]" LOC = G15;
#NET "ser[19]" LOC = A19;
NET "des[12]" LOC = G16;
NET "tx_error" LOC = M16;
NET "des[13]" LOC = G14;
#NET "cntrl0_ddr2_ck_n[0]" LOC = AA2;
NET "des[14]" LOC = H14;
NET "l2p_rdy" LOC = P16;
#NET "cntrl0_ddr2_ck_n[1]" LOC = Y2;
#NET "cntrl0_ddr2_a[0]" LOC = D3;
NET "des[15]" LOC = H13;
NET "l2p_valid" LOC = T19;
#NET "cntrl0_ddr2_a[1]" LOC = G5;
NET "des[16]" LOC = F12;
#NET "cntrl0_ddr2_dq[0]" LOC = W1;
#NET "cntrl0_ddr2_a[2]" LOC = G6;
NET "des[17]" LOC = G12;
#NET "cntrl0_ddr2_dq[1]" LOC = W2;
#NET "sys_clkb" LOC = U12;
NET "l2p_data[10]" LOC = R19;
#NET "cntrl0_ddr2_a[3]" LOC = E1;
NET "des[18]" LOC = D11;
#NET "cntrl0_ddr2_dq[2]" LOC = U3;
NET "p2l_valid" LOC = M22;
NET "l2p_data[11]" LOC = N18;
#NET "cntrl0_ddr2_a[4]" LOC = D1;
NET "des[19]" LOC = C5;
#NET "cntrl0_ddr2_dq[3]" LOC = U4;
NET "l2p_data[12]" LOC = U19;
#NET "cntrl0_ddr2_a[5]" LOC = E3;
#NET "cntrl0_ddr2_dq[4]" LOC = V1;
NET "l2p_data[13]" LOC = U21;
#NET "cntrl0_ddr2_a[6]" LOC = F4;
#NET "cntrl0_ddr2_dq[5]" LOC = V3;
NET "des[0]" LOC = A8;
NET "l2p_data[14]" LOC = U20;
#NET "cntrl0_ddr2_a[7]" LOC = G4;
#NET "cntrl0_ddr2_dq[6]" LOC = U1;
NET "des[1]" LOC = D10;
NET "l2p_edb" LOC = L21;
NET "l2p_data[15]" LOC = N19;
#NET "cntrl0_ddr2_a[8]" LOC = F3;
#NET "cntrl0_ddr2_dq[7]" LOC = U2;
NET "des[2]" LOC = E10;
#NET "cntrl0_ddr2_a[9]" LOC = H6;
#NET "cntrl0_ddr2_dq[8]" LOC = R5;
NET "des[3]" LOC = H10;
#NET "cntrl0_ddr2_dq[9]" LOC = T3;
NET "des[4]" LOC = B9;
NET "des[5]" LOC = B8;
NET "p_rd_d_rdy[0]" LOC = N17;
NET "p_rd_d_rdy[1]" LOC = P18;
NET "des[6]" LOC = C8;
NET "des[7]" LOC = G10;
NET "l_rst_n" LOC = N20;
NET "p2l_data[10]" LOC = K19;
NET "p_wr_rdy[0]" LOC = T20;
NET "p_wr_rdy[1]" LOC = T22;
NET "des[8]" LOC = A7;
NET "p2l_data[11]" LOC = M20;
NET "des[9]" LOC = A6;
NET "p2l_data[12]" LOC = G22;
NET "p2l_data[13]" LOC = L18;
NET "p2l_data[14]" LOC = M18;
NET "p2l_rdy" LOC = D21;
NET "p2l_data[15]" LOC = K20;
NET "l2p_clkn" LOC = Y21;
NET "l2p_clkp" LOC = AA22;
#NET "ser[0]" LOC = D17;
#NET "ser[1]" LOC = C17;
NET "des_dvb_asi" LOC = E13;
#NET "ser[2]" LOC = D16;
NET "debug[0]" LOC = AB11;
NET "syncseperator_v_timing" LOC = B6;
#NET "ser[3]" LOC = C16;
NET "rx_error" LOC = U22;
NET "des_smpte_bypass" LOC = A13;
NET "debug[1]" LOC = Y11;
#NET "ser[4]" LOC = C14;
NET "debug[2]" LOC = R10;
#NET "ser[5]" LOC = E14;
NET "debug[3]" LOC = AB10;
#NET "ser[6]" LOC = B17;
NET "debug[4]" LOC = U7;
#NET "ser[7]" LOC = A17;
NET "debug[5]" LOC = V7;
#NET "ser[8]" LOC = D15;
NET "debug[6]" LOC = U8;
#NET "ser[9]" LOC = C15;
NET "debug[7]" LOC = T9;
NET "vc_rdy[0]" LOC = N21;
NET "vc_rdy[1]" LOC = L20;
NET "mic_data[0]" LOC = AB15;
NET "mic_data[1]" LOC = Y17;
#NET "cntrl0_ddr2_we_n" LOC = G17;
NET "mic_data[2]" LOC = AA14;
NET "mic_data[3]" LOC = AA19;
#NET "cntrl0_ddr2_odt" LOC = G18;
#NET "cntrl0_ddr2_a[10]" LOC = H5;
#NET "sys_clk" LOC = V12;
NET "p2l_clkn" LOC = E12;
NET "p2l_clkp" LOC = C12;
NET "mic_data[4]" LOC = Y16;
#NET "cntrl0_ddr2_a[11]" LOC = J5;
NET "l_wr_rdy[0]" LOC = M17;
NET "l_wr_rdy[1]" LOC = R15;
NET "mic_data[5]" LOC = Y7;
#NET "cntrl0_ddr2_dq[10]" LOC = R3;
#NET "cntrl0_ddr2_ck[0]" LOC = AA1;
#NET "cntrl0_ddr2_a[12]" LOC = K6;
NET "mic_data[6]" LOC = AB17;
#NET "cntrl0_ddr2_dq[11]" LOC = R4;
#NET "cntrl0_ddr2_ck[1]" LOC = Y1;
NET "mic_data[7]" LOC = AB19;
NET "l2p_data[0]" LOC = V22;
#NET "cntrl0_ddr2_dq[12]" LOC = M5;
NET "mic_data[8]" LOC = AB6;
NET "l2p_data[1]" LOC = W22;
NET "cntrl0_ddr2_dq[13]" LOC = N4;
#NET "cntrl0_ddr2_dqs_n[0]" LOC = U5;
#NET "cntrl0_ddr2_cas_n" LOC = N3;
NET "mic_data[9]" LOC = AB8;
NET "l2p_data[2]" LOC = V20;
NET "l_clkn" LOC = V11;
#NET "cntrl0_ddr2_dq[14]" LOC = P3;
NET "p2l_data[0]" LOC = E22;
NET "l_clkp" LOC = U11;
#NET "cntrl0_ddr2_dqs_n[1]" LOC = R2;
NET "des_sdhdn" LOC = A14;
NET "l2p_data[3]" LOC = V19;
#NET "cntrl0_ddr2_dq[20]" LOC = L5;
#NET "cntrl0_ddr2_dq[15]" LOC = P5;
NET "p2l_data[1]" LOC = J18;
#NET "cntrl0_ddr2_dqs_n[2]" LOC = L1;
NET "l2p_data[4]" LOC = W21;
#NET "cntrl0_ddr2_dq[21]" LOC = L3;
#NET "cntrl0_ddr2_dq[16]" LOC = M3;
NET "p2l_data[2]" LOC = G19;
#NET "cntrl0_ddr2_dqs_n[3]" LOC = H3;
NET "l2p_data[5]" LOC = Y22;
#NET "cntrl0_ddr2_dq[22]" LOC = K3;
#NET "cntrl0_ddr2_dq[17]" LOC = M4;
NET "p2l_data[3]" LOC = K15;
NET "mic_data[10]" LOC = W8;
NET "l2p_data[6]" LOC = T18;
#NET "cntrl0_ddr2_dq[23]" LOC = K2;
#NET "cntrl0_ddr2_dq[18]" LOC = M1;
NET "p2l_data[4]" LOC = H17;
NET "mic_data[11]" LOC = V16;
NET "l2p_data[7]" LOC = T17;
NET "syncseperator_h_timing" LOC = C7;
#NET "cntrl0_ddr2_dq[24]" LOC = K5;
#NET "cntrl0_ddr2_dq[19]" LOC = M2;
NET "p2l_data[5]" LOC = G20;
NET "mic_data[12]" LOC = AA6;
NET "l2p_data[8]" LOC = W20;
#NET "cntrl0_ddr2_dq[30]" LOC = F2;
#NET "cntrl0_ddr2_dq[25]" LOC = K4;
NET "p2l_data[6]" LOC = F22;
NET "mic_data[13]" LOC = Y8;
NET "l2p_data[9]" LOC = W19;
#NET "cntrl0_ddr2_dq[31]" LOC = F1;
#NET "cntrl0_ddr2_dq[26]" LOC = J3;
NET "p2l_data[7]" LOC = H19;
NET "mic_data[14]" LOC = Y6;
#NET "cntrl0_ddr2_ras_n" LOC = D2;
#NET "cntrl0_rst_dqs_div_out" LOC = P1;
#NET "cntrl0_ddr2_dq[27]" LOC = H1;
NET "p2l_data[8]" LOC = K22;
NET "mic_data[20]" LOC = AA15;
NET "mic_data[15]" LOC = V15;
#NET "cntrl0_ddr2_dq[28]" LOC = G3;
NET "p2l_data[9]" LOC = K17;
NET "mic_data[21]" LOC = Y12;
NET "mic_data[16]" LOC = AB16;
#NET "cntrl0_ddr2_dq[29]" LOC = G1;
#NET "cntrl0_ddr2_ba[0]" LOC = B1;
NET "mic_data[22]" LOC = AB21;
NET "mic_data[17]" LOC = W17;
#NET "cntrl0_ddr2_ba[1]" LOC = E4;
NET "mic_data[23]" LOC = Y13;
NET "mic_data[18]" LOC = V14;
NET "reset_in_n" LOC = N8;
#NET "cntrl0_rst_dqs_div_in" LOC = P2;
NET "mic_data[24]" LOC = U13;
NET "mic_data[19]" LOC = Y5;
NET "gpio[10]" LOC = AB18;
NET "mic_data[30]" LOC = AB14;
NET "mic_data[25]" LOC = W18;
NET "gpio[11]" LOC = Y10;
NET "mic_data[31]" LOC = W16;
NET "mic_data[26]" LOC = W15;
NET "l2p_dframe" LOC = J22;
NET "gpio[12]" LOC = W6;
NET "mic_data[27]" LOC = Y18;
#NET "cntrl0_ddr2_dm[0]" LOC = T4;
#NET "cntrl0_ddr2_cke" LOC = C2;
NET "gpio[13]" LOC = Y9;
NET "mic_data[28]" LOC = AB7;
#NET "cntrl0_ddr2_dm[1]" LOC = H2;
NET "gpio[14]" LOC = AB9;
NET "mic_data[29]" LOC = AA21;
#NET "cntrl0_ddr2_dm[2]" LOC = V4;
NET "gpio[15]" LOC = AA10;
#NET "cntrl0_ddr2_dm[3]" LOC = W3;
NET "des_pclk" LOC = E11;
NET "sda" LOC = A16; ##R12; ##Problem
#NET "mic_clka" LOC = Y15;
#NET "mic_clkb" LOC = Y4;
NET "scl" LOC = W9;
NET "gpio[0]" LOC = AB5;
#NET "ser[10]" LOC = E17;
NET "l_rst33_n" LOC = H8;
NET "gpio[1]" LOC = W7;
#NET "ser[11]" LOC = D18;
NET "gpio[2]" LOC = AB4;
#NET "ser[12]" LOC = C19;
#NET "cntrl0_ddr2_dqs[0]" LOC = T5;
NET "gpio[3]" LOC = AB3;
#NET "ser[13]" LOC = B20;
#NET "cntrl0_ddr2_dqs[1]" LOC = R1;
NET "des_f" LOC = A10;
#NET "ser_h" LOC = D8;
#NET "ser_v" LOC = A12;
#NET "ser_f" LOC = D13;
#NET "ser_smpte_bypass" LOC = C6;
#NET "ser_dvb_asi" LOC = A3;
#NET "ser_sdhdn" LOC = E9;
NET "p_wr_req[0]" LOC = L15;
NET "p_wr_req[1]" LOC = R21;
NET "led[0]" LOC = Y14;
NET "led[1]" LOC = W12;
NET "led[2]" LOC = V17;
NET "led[3]" LOC = AA17;
NET "led[4]" LOC = AA12;
NET "led[5]" LOC = AB12;
NET "led[6]" LOC = V9;
NET "led[7]" LOC = W13;
NET "spi_sck" LOC = G9;
NET "spi_ss[0]" LOC = D5;
NET "spi_ss[1]" LOC = B13;
NET "spi_ss[2]" LOC = A4;
NET "spi_ss[3]" LOC = C13;
NET "spi_ss[4]" LOC = B15;
NET "spi_mosi" LOC = G13;
NET "spi_miso" LOC = A5;
NET "gs4911_host_B" LOC = B4;
NET "gs4911_sclk" LOC = B3;
NET "gs4911_sdin" LOC = D6;
NET "gs4911_sdout" LOC = E8;
NET "gs4911_csb" LOC = A9;
NET "PCLK_4911_1531" LOC = A11;
NET "GS4911_LOCK_LOST" LOC = B22;
NET "GS4911_REF_LOST" LOC = B21;
#---------------------------------------------------------------------------------------------
# Prohibit the use of configuration pins
#---------------------------------------------------------------------------------------------
CONFIG CONFIG_MODE=S_SERIAL;
CONFIG PROHIBIT = W5; # MODE 0
CONFIG PROHIBIT = V6; # MODE 1
CONFIG PROHIBIT = W4; # MODE 2
CONFIG PROHIBIT = V13; # INIT_B
CONFIG PROHIBIT = AB20; # DIN
CONFIG PROHIBIT = AA20; # CCLK
CONFIG PROHIBIT = J1;
CONFIG PROHIBIT = N1;
CONFIG PROHIBIT = T1;
CONFIG PROHIBIT = J8;
CONFIG PROHIBIT = R6;
CONFIG PROHIBIT = H7;
CONFIG PROHIBIT = L8;
CONFIG PROHIBIT = T6;
CONFIG PROHIBIT = R12;
CONFIG PROHIBIT = R13;
CONFIG PROHIBIT = R14;
CONFIG PROHIBIT = T10;
CONFIG PROHIBIT = T11;
CONFIG PROHIBIT = T15;
CONFIG PROHIBIT = T16;
CONFIG PROHIBIT = T7;
CONFIG PROHIBIT = T8;
CONFIG PROHIBIT = V8;
CONFIG PROHIBIT = P22;
CONFIG PROHIBIT = R16;
CONFIG PROHIBIT = R18;
CONFIG PROHIBIT = N16;
CONFIG PROHIBIT = M15;
CONFIG PROHIBIT = K14;
CONFIG PROHIBIT = J15;
CONFIG PROHIBIT = H16;
CONFIG PROHIBIT = A15;
CONFIG PROHIBIT = C9;
CONFIG PROHIBIT = D19;
CONFIG PROHIBIT = B19;
CONFIG PROHIBIT = B2;
CONFIG PROHIBIT = G8;
CONFIG PROHIBIT = H12;
CONFIG PROHIBIT = H9;
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_32x512.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_32x512.vhd when simulating
-- the core, fifo_32x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_32x512 IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
END fifo_32x512;
ARCHITECTURE fifo_32x512_a OF fifo_32x512 IS
-- synthesis translate_off
component wrapped_fifo_32x512
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_32x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 32,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 32,
c_msgon_val => 1,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 508,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 509,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 4,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_32x512
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full);
-- synthesis translate_on
END fifo_32x512_a;
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##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Thu Sep 23 08:35:20 2010
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s1400a
SET devicefamily = spartan3a
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -5
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=fifo_32x512
CSET data_count=false
CSET data_count_width=9
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_negate_value=3
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=509
CSET full_threshold_negate_value=508
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=32
CSET input_depth=512
CSET output_data_width=32
CSET output_depth=512
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=Multiple_Programmable_Full_Threshold_Input_Ports
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=9
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=true
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=9
# END Parameters
GENERATE
# CRC: ce29be58
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="fifo_32x512.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="fifo_32x512.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="fifo_32x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s1400a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|fifo_32x512|fifo_32x512_a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="fifo_32x512.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_32x512" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fg484" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_32x512" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-09-23T10:35:27" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="134B851861F96372525873D4E7767890" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_64x512.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_64x512.vhd when simulating
-- the core, fifo_64x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_64x512 IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(63 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
END fifo_64x512;
ARCHITECTURE fifo_64x512_a OF fifo_64x512 IS
-- synthesis translate_off
component wrapped_fifo_64x512
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(63 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_64x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 64,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 64,
c_msgon_val => 1,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 508,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 509,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x72",
c_count_type => 0,
c_prog_full_type => 4,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_64x512
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full);
-- synthesis translate_on
END fifo_64x512_a;
hdl/gn4124core/design/ipcore_dir/fifo_64x512.xco 0 → 100644
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##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Thu Sep 23 08:42:15 2010
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s1400a
SET devicefamily = spartan3a
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -5
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=fifo_64x512
CSET data_count=false
CSET data_count_width=9
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_negate_value=3
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=509
CSET full_threshold_negate_value=508
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=64
CSET input_depth=512
CSET output_data_width=64
CSET output_depth=512
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=Multiple_Programmable_Full_Threshold_Input_Ports
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=9
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=true
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=9
# END Parameters
GENERATE
# CRC: bbf199eb
hdl/gn4124core/design/ipcore_dir/fifo_64x512.xise 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="fifo_64x512.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="fifo_64x512.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="fifo_64x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s1400a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|fifo_64x512|fifo_64x512_a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="fifo_64x512.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_64x512" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fg484" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_64x512" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-09-23T10:42:21" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="39408F1BAE3A8081592B702FA80F00A3" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
hdl/gn4124core/design/ipcore_dir/ram_2048x32.gise 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ram_2048x32.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
hdl/gn4124core/design/ipcore_dir/ram_2048x32.mif 0 → 100644
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00000000000000000001000100010001
00000000000000000001000100010001
00000000000000000001000100010001
00000000000000000001000100010001
00000000000000000001000100010001
00000000000000000000000000000000
00000000000000000000000100000001
00000000000000000000000000010001
00000000000000000000000000000000
00000000000000000001000100010001
00000000000000000001000100010001
00000000000000000001000100010001
00000000000000000001000100010001
00000000000000000001000100010001
00000000000000000001000100010001
00000000000000000001000100010001
hdl/gn4124core/design/ipcore_dir/ram_2048x32.ncf 0 → 100644
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− 0
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hdl/gn4124core/design/ipcore_dir/ram_2048x32.ngc 0 → 100644
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hdl/gn4124core/design/ipcore_dir/ram_2048x32.vhd 0 → 100644
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file ram_2048x32.vhd when simulating
-- the core, ram_2048x32. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY ram_2048x32 IS
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(10 downto 0);
dina: IN std_logic_VECTOR(31 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0));
END ram_2048x32;
ARCHITECTURE ram_2048x32_a OF ram_2048x32 IS
-- synthesis translate_off
component wrapped_ram_2048x32
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(10 downto 0);
dina: IN std_logic_VECTOR(31 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0));
end component;
-- Configuration specification
for all : wrapped_ram_2048x32 use entity XilinxCoreLib.blk_mem_gen_v4_2(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 32,
c_initb_val => "0",
c_family => "spartan3",
c_read_width_a => 32,
c_disable_warn_bhv_coll => 0,
c_use_softecc => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "/home/mcattin/projects/GN4124_core/GennumCore/Gn4124core/design/ipcore_dir/ram_2048x32.mif",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_softecc_output_regs_b => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 1,
c_xdevicefamily => "spartan3a",
c_write_depth_b => 2048,
c_write_depth_a => 2048,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 11,
c_has_softecc_input_regs_a => 0,
c_addrb_width => 11,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 32,
c_write_width_a => 32,
c_read_depth_b => 2048,
c_read_depth_a => 2048,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_ram_2048x32
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- synthesis translate_on
END ram_2048x32_a;
hdl/gn4124core/design/ipcore_dir/ram_2048x32.xco 0 → 100644
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##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Mon Oct 4 13:58:49 2010
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s1400a
SET devicefamily = spartan3a
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -5
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 4.2
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=./ram_2048x32_init.coe
CSET collision_warnings=ALL
CSET component_name=ram_2048x32
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET load_init_file=true
CSET memory_type=Single_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=0
CSET port_b_enable_rate=0
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=32
CSET read_width_b=32
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=2048
CSET write_width_a=32
CSET write_width_b=32
# END Parameters
GENERATE
# CRC: d12ee861
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